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參數(shù)資料
| 型號： | MC145202-1 |
| 廠商： | Motorola, Inc. |
| 英文描述： | PLL Frequency Synthesizer(2.0GHz PLL頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成器（2.0GHz的鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 14/23頁 |
| 文件大?。?/td> | 270K |
| 代理商： | MC145202-1 |
M
1
M
S
A22
A21
A20
A19
A17
A15
A13
A12
A11
A10
A7
A6
A5
A4
A3
A1
Note 3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
1
1
MSB
LSB
0
0
1
1
0
1
0
1
Port
Data Out
f
f
R
V
Binary
Value
Output A
Function
(Note 1)
Both Bits
Must Be
High
0
0
0
0
0
0
0
0
.
F
F
0
0
0
0
0
0
0
0
.
F
F
0
1
2
3
4
5
6
7
.
E
F
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
N COUNTER = 5
N COUNTER = 6
N COUNTER = 7
N COUNTER = 4094
N COUNTER = 4095
Hexadecimal Value
For N Counter
0
0
0
0
.
3
3
4
0
1
2
3
.
E
F
0
A COUNTER =
A COUNTER =
A COUNTER =
A COUNTER =
0
1
2
3
A COUNTER =
A COUNTER =
Not Allowed
62
63
÷
÷
4
.
1
.
Not Allowed
Hexadecimal Value
For A Counter
F
F
Not Allowed
÷
÷
÷
÷
NOTES:
1. A power-on initialize circuit forces the Output A function to default to Data Out.
2. The values programmed for the N counter must be greater than or equal to the values programmed for the A counter. This results in a total divide value = N x 64 + A.
3. At this point, the three new bytes are transferred to the A register. In addition, the 13 LSBs in the first buffer of the R register are transferred to the R register’s second buffer.
Thus, the R, N, and A counters can be presented new divide ratios at the same time. The first buffer of the R register is not affected. The C register is not affected.
ENB
CLK
Din
F
Figure 15. A Register Access and Format
(24 Clock Cycles are Used)
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