參數(shù)資料
型號(hào)： MB90P678
廠商： Fujitsu Limited
英文描述： 16-Bit Proprietary Microcontroller(16位專用微控制器)
中文描述： 16位微控制器專利（16位專用微控制器）
文件頁(yè)數(shù)： 70/111頁(yè)
文件大?。?/td> 736K
代理商： MB90P678
MB90670/675 Series
70
4. AC Characteristics
(1) Clock Timing
When V
CC
= +5.0 V
±
10%
(V
CC
= +4.5 V to +5.5 V, V
SS
= 0.0 V, T
A
= –40
°
C to +85
°
C)
Value
Min.
Max.
—
3
32
—
31.25
333
* :The frequency fluctuation ratio indicates the maximum fluctuation ratio from the set center frequency while locked
when using the PLL multiplier.
When V
CC
= +2.7 V (min.)
(V
CC
= +2.7 V to +5.5 V, V
SS
= 0.0 V, T
A
= –40
°
C to +85
°
C)
Value
Min.
Max.
—
3
16
—
62.5
333
* :The frequency fluctuation ratio indicates the maximum fluctuation ratio from the set center frequency while locked
when using the PLL multiplier.
Parameter
Symbol
Pin name
Condition
Unit
Remarks
Source oscillation frequency
Source oscillation cycle time
F
C
t
C
P
WH
P
WL
t
CR
t
CF
f
CP
t
CP
X0, X1
X0, X1
MHz
ns
Input clock pulse width
X0
—
10
—
ns
Use duty ratio 30 to
70% as a guide.
Input clock rising/falling time
X0
—
—
5
ns
Internal operation clock frequency
Internal operation clock cycle time
When frequency fluctuation
is locked
—
—
—
—
1.5
62.5
16
666
MHz
ns
f
P37/CLK
—
—
3
%
*
Parameter
Symbol
Pin name
Condition
Unit
Remarks
Source oscillation frequency
Source oscillation cycle time
F
C
t
C
P
WH
P
WL
t
CR
t
CF
f
CP
t
CP
X0, X1
X0, X1
MHz
ns
Input clock pulse width
X0
—
20
—
ns
Use duty ratio 30 to
70% as a guide.
Input clock rising/falling time
X0
—
—
5
ns
Internal operation clock frequency
Internal operation clock cycle time
When frequency fluctuation
ratio is locked
—
—
—
—
1.5
125
8
MHz
ns
666
f
P37/CLK
—
—
3
%
*
+
—
Center frequency
+
α
–
α
f
O
f =
α
f
O
×
100 (%)
Because the PLL frequency fluctuates around the set frequency with a certain cycle [approximately CLK
×
(1 to 50 CYC)], the worst value is not maintained for long. (The pulse, if featured with the long period, would
produce practically no error.)
+
—
Center frequency
+
α
–
α
f
O
f =
α
f
O
×
100 (%)
Because the PLL frequency fluctuates around the set frequency with a certain cycle [approximately CLK
×
(1 to 50 CYC)], the worst value is not maintained for long. (The pulse, if featured with the long period, would
produce practically no error.)
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