
MB90670/675 Series
42
3. UART1 (SCI)
The UART is a serial I/O port used for CLK asynchronous (start-stop synchronization) communications or for
CLK synchronous (I/O extended serial) communications. The features of this module are described below:
Full-duplex double buffer
CLK asynchronous (start-stop synchronization) communications and CLK synchronous (I/O extended serial)
communications capable
Supports multiprocessor mode
Built-in dedicated baud rate generator
CLK asynchronous: 62500, 31250, 19230, 9615, 4808, 2404 and 1202 bps
CLK synchronous: 2 Mbps, 1 Mbps, 500 Kbps, and 250 Kbps
Permits setting of any desired baud rate according to an external clock input
Error detection function (parity errors, framing errors, and overrun errors)
NRZ code as transfer signal
Supports Intelligent I/O Service
(1) Register Configuration
MD1
MD0
CS2
CS1
CS0
BCH SCKE SOE
SMR
Serial mode register 1
Address : channel 1 000024
H
Serial control register 1
Address : channel 1 000025
H
Serial status register 1
Address : channel 1 000027
H
Serial input data register 1/
Serial output data register 1
Address : channel 1 000026
H
PEN
P
SBL
CL
A/D
REC
RXE
TXE
D7
D6
D5
D4
D3
D2
D1
D0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
PE
ORE
FRE RDRF TDRE
—
RIE
TIE
←
Bit no.
SCR
←
Bit no.
SSR
←
Bit no.
SIDR (read)/
SODR (write)
←
Bit no.
15
14
13
12
11
10
9
8
Read/write
→
Initial value
→
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Read/write
→
Initial value
→
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(1)
(—)
(—)
(R/W)
(0)
(R/W)
(0)
Read/write
→
Initial value
→
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Read/write
→
Initial value
→
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
(R/W)
(0)
(R/W)
(0)