參數(shù)資料
型號(hào)： MB90P678
廠商： Fujitsu Limited
英文描述： 16-Bit Proprietary Microcontroller(16位專用微控制器)
中文描述： 16位微控制器專利（16位專用微控制器）
文件頁(yè)數(shù)： 64/111頁(yè)
文件大?。?/td> 736K
代理商： MB90P678
MB90670/675 Series
64
14. Watchdog Timer and Timebase Timer Functions
The watchdog timer consists of a 2-bit watchdog counter that uses the carry signal from the 18-bit timebase
timer as a clock source, a watchdog timer control register, and a watchdog reset controller.
The timebase timer consists of an 18-bit timer and a circuit that controls interval interrupts. Note that the time-
base timer uses the main clock, regardless of the setting of the MCS bit in CKSCR.
(1) Register Configuration
(2) Block Diagram
Address : 0000A8
H
PONR STBR WRSTERST SRST WTE WT1
WT0
WDTC
7
6
5
4
3
2
1
0
Read/write
→
Initial value
→
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(W)
(1)
(W)
(1)
(W)
(1)
←
Bit no.
Watchdog timer control register
Address : 0000A9
H
Reserved
—
—
TBIE TBOF TBR TBC1 TBC0
TBTC
15
14
13
12
11
10
9
8
Read/write
→
Initial value
→
(—)
(1)
(—)
(—)
(—)
(—)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
(R/W)
(0)
(R/W)
(0)
←
Bit no.
Timebase timer control register
TBTC
PONR
STBR
WRST
ERST
SRST
TBC0
TBR
TBIE
TBOF
TBC1
WT1
WT0
WTE
WDTC
Selector
Selector
AND
CLR
OF
2-bit counter
CLR
Watchdog reset
generator
WDGRST
To internal reset
generator
From power-on generation
From hardware standby
controller
RST pin
From RST bit in
the LPMCR register
Timebase interrupt
Clock input
2
12
2
14
2
16
2
19
TBTRES
Timebase timer
2
12
2
14
2
16
2
19
Main clock
(OSC oscillation)
2
M
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