
65
MB90670/675 Series
15. Low-power Consumption Controller (CPU Intermittent Operation Function, Oscillation
Stabilization Delay Time, Clock Multiplier Function)
The following are the operating modes: PLL clock mode, PLL sleep mode, watch mode, main clock mode, main
sleep mode, stop mode, and hardware standby mode. Aside from the PLL clock mode, all of the other operating
modes are low power consumption modes.
In main clock mode and main sleep mode, only the main clock (main OSC oscillation clock) operates. In these
modes, the main clock divided by 2 is used as the operation clock, and the PLL clock (VCO oscillation clock) is
stopped.
In PLL sleep mode and main sleep mode, only the CPU’s operation clock is stopped; all clocks other than the
CPU clock operate.
In watch mode, only the time-base timer operates.
The stop mode and hardware standby mode stop oscillation, making it possible to retain data while consuming
the least amount of power .
The CPU intermittent operation function intermittently runs the clock supplied to the CPU when accessing
registers, on-chip memory, on-chip resources, and the external bus. Processing is possible with lower power
consumption by reducing the execution speed of the CPU while supplying a high-speed clock and using on-chip
resources.
The PLL clock multiplier can be selected as either 1, 2, 3, or 4 by setting the CS1 and CS0 bits.
The WS1 and WS0 bits can be used to set the main clock oscillation stabilization delay time for when stop mode
and hardware standby mode are woken up.
(1) Register Configuration
Address : 0000A0
H
STP
SLP
SPL
RST
Reserved
CG1
CG0
Reserved
LPMCR
7
6
5
4
3
2
1
0
Read/write
→
Initial value
→
(W)
(0)
(W)
(0)
(R/W)
(0)
(W)
(1)
(—)
(1)
(R/W)
(0)
(R/W)
(0)
(—)
(0)
←
Bit no.
Low-power consumption
mode control register
Address : 0000A1
H
Reserved
MCM WS1 WS0
Reserved
MCS CS1
CS0
CKSCR
15
14
13
12
11
10
9
8
Read/write
→
Initial value
→
(—)
(1)
(R)
(1)
(R/W)
(1)
(R/W)
(1)
(—)
(1)
(R/W)
(1)
(R/W)
(0)
(R/W)
(0)
←
Bit no.
Clock selection register