
51
MB90670/675 Series
7. 24-bit Free-run Timer
The 24-bit free-run timer consists of a 24-bit up counter, an 8-bit output buffer, and a free-run timer control
register. The counter value output from this free-run timer is used for basic time generation by the input capture
and output compare units.
The interrupt functions are the timer overflow interrupt and timer intermediate bit interrupt; four different time
settings can be made for the intermediate bit interrupt.
A reset clears the timer counter value for the 24-bit free-run timer to all zeroes.
(1) Register Configuration
—
—
Reserved Reserved Reserved Reserved Reserved
PR0
Free-run timer control register upper
Address : 000051
H
Free-run timer control register lower
Address : 000050
H
Free run timer lower
16-bit data register lower
Address : 000054
H
Free-run timer lower
16-bit data register upper
Address : 000055
H
STP
CLR
IVF
IVFE
TIM
TIME
TIS1
TIS0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
←
Bit no.
TCCR
TCCR
←
Bit no.
TCRL
TCRL
←
Bit no.
←
Bit no.
15
14
13
12
11
10
9
8
Read/write
→
Initial value
→
(—)
(—)
(—)
(—)
(—)
(1)
(—)
(1)
(—)
(1)
(—)
(1)
(—)
(1)
(R/W)
(1)
Read/write
→
Initial value
→
(R)
(0)
15
(R)
(0)
14
(R)
(0)
13
(R)
(0)
12
(R)
(0)
11
(R)
(0)
10
(R)
(0)
9
(R)
(0)
8
Free-run timer upper
8-bit data register upper
Address : 000057
H
←
Bit no.
Read/write
→
Initial value
→
(R)
(0)
7
(R)
(0)
6
(R)
(0)
5
(R)
(0)
4
(R)
(0)
3
(R)
(0)
2
(R)
(0)
1
(R)
(0)
0
Read/write
→
Initial value
→
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
Read/write
→
Initial value
→
(W)
(1)
(W)
(1)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Free run timer upper
8-bit data register lower
Address : 000056
H
TCRH
TCRH
←
Bit no.
Read/write
→
Initial value
→
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)