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MB90560 series
Figure 11.6-2
Event counter mode setting ................................................................................................ 264
Figure 11.6-3
Counter status transition ..................................................................................................... 265
Figure 11.6-4
Count operation in reload mode (software trigger operation) ............................................. 266
Figure 11.6-5
Counting in reload mode (external trigger operation) ......................................................... 267
Figure 11.6-6
Count operation in reload mode (software trigger and gate input operation) ..................... 267
Figure 11.6-7
Count operation in single-shot mode (software trigger operation) ...................................... 268
Figure 11.6-8
Count operation in single-shot mode (external trigger operation) ...................................... 269
Figure 11.6-9
Count operation in single-shot mode (software trigger and gate input operation) .............. 269
Figure 11.6-10
Count operation in reload mode (event count mode) ......................................................... 270
Figure 11.6-11
Counter operation in single-shot mode (event count mode) ............................................... 271
Figure 12.2-1
BLock Diagram of Realtime I/O .......................................................................................... 280
Figure 12.2-2
Block Diagram of 8/16-bit PPG Timer ................................................................................ 281
Figure 12.2-3
Block Diagram of Waveform Generator .............................................................................. 282
Figure 12.3-1
Registers of 16-bit Free-Run Timer .................................................................................... 284
Figure 12.3-2
Registers of Output Compare ............................................................................................. 285
Figure 12.3-3
Registers of 16-bit Input Capture ........................................................................................ 286
Figure 12.3-4
Registers of 8/16-bit PPG Timers ....................................................................................... 287
Figure 12.3-5
Registers of Waveform Generator ...................................................................................... 288
Figure 12.3.1-1 Registers of 16-bit Free-Run Timer .................................................................................... 290
Figure 12.3.1.1-1Compare Clear Register (CPCR) ....................................................................................... 291
Figure 12.3.1.2-1Timer Data Register ........................................................................................................... 292
Figure 12.3.1.3-1Timer Control Status Register (Upper) ............................................................................... 294
Figure 12.3.1.3-2Timer Control Status Register (Lower) ............................................................................... 296
Figure 12.3.2-1 Registers of Output Compare ............................................................................................. 298
Figure 12.3.2.1-1Compare Registers (OCCP0~5) ......................................................................................... 299
Figure 12.3.2.2-1Compare Control Register (Upper, OSC1/3/5) ................................................................... 300
Figure 12.3.2.2-2Compare Control Register (Lower, OSC0/2/4) ................................................................... 302
Figure 12.3.3-1 Registers of 16-bit Input Capture ........................................................................................ 304
Figure 12.3.3.1-1Input Capture Registers (IPCP0~3) .................................................................................... 305
Figure 12.3.3.2-1Capture Control Register (ICS23) ...................................................................................... 306
Figure 12.3.3.2-2Capture Control Register (ICS01) ...................................................................................... 308
Figure 12.3.4-1 Registers of 8/16-bit PPG Timers ....................................................................................... 310
Figure 12.3.4.1-1PPG Reload Register (PRLH0~5, PRLL0~5) ..................................................................... 311
Figure 12.3.4.2-1PPG1/3/5 Control Register (PPGC1/3/5) ........................................................................... 312
Figure 12.3.4.2-2PPG0/2/4 Control Register (PPGC0/2/4) ........................................................................... 314
Figure 12.3.4.3-1PPG0/1/2/3/4/5 Clock Control Register (PCD01/23/45) ..................................................... 316
Figure 12.3.5-1 Registers of Waveform Generator ...................................................................................... 318
Figure 12.3.5.1-18-bit Reload Registers (TMRR0/1/2) .................................................................................. 319