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MB90560 series
xi
Figure 6.6-1
Extended intelligent I/O service (EI2OS) operation .............................................................147
Figure 6.6-2
Configuration of EI2OS descriptor (ISD) .............................................................................148
Figure 6.6-3
Configuration of DCT ...........................................................................................................150
Figure 6.6-4
Configuration of I/O register address pointer (IOA) .............................................................150
Figure 6.6-5
Configuration of EI2OS status register (ISCS) ....................................................................151
Figure 6.6-6
Configuration of buffer address pointer (BAP) ....................................................................152
Figure 6.7-1
Flow of extended intelligent I/O service (EI2OS) operation .................................................154
Figure 6.7-1
Procedure for using the extended intelligent I/O service (EI2OS) .......................................155
Figure 6.9-1
Stack operations at the start of interrupt processing ...........................................................160
Figure 6.9-2
Stack area ...........................................................................................................................161
Figure 7.1-1
Mode classification ..............................................................................................................168
Figure 7.3-1
Mode data configuration ......................................................................................................170
Figure 7.3-2
Correspondence between access areas and physical addresses in single-chip mode ......171
Figure 8.3-1
Block diagram of port 0 pins ................................................................................................177
Figure 8.4-1
Block diagram of port 1 pins ................................................................................................183
Figure 8.5-1
Block diagram of port 2 pins ................................................................................................189
Figure 8.6-1
Block diagram of port 3 pins ................................................................................................195
Figure 8.7-1
Block diagram of port 4 pins ................................................................................................201
Figure 8.8-1
Block diagram of port 5 pins ................................................................................................207
Figure 8.9-1
Block diagram of port 6 pins ................................................................................................213
Figure 8.10-1
Example of eight-segment LED connection ........................................................................218
Figure 9.2-1
Block diagram of the timebase timer ...................................................................................224
Figure 9.3-1
Timebase timer control register (TBTC) ..............................................................................226
Figure 9.5-1
Setting of the timebase timer ...............................................................................................230
Figure 9.6-1
Effect on PPG when clearing timebase timer ......................................................................232
Figure 9.6-2
Timebase timer operations ..................................................................................................233
Figure 10.2-1
Block diagram of the watchdog timer ..................................................................................239
Figure 10.3-1
Watchdog timer control register (WDTC) ............................................................................240
Figure 10.4-1
Setting of the watchdog timer ..............................................................................................242
Figure 10.4-2
Clear timing and watchdog timer intervals ..........................................................................243
Figure 11.2-1
Block diagram of the 16-bit reload timer ..............................................................................252
Figure 11.3-1
Block diagram of the 16-bit reload timer pins ......................................................................254
Figure 11.4-1
16-bit reload timer registers .................................................................................................255
Figure 11.4-2
Timer control status register, upper part (TMCSR0, TMCSR1: H) .....................................256
Figure 11.4-3
Timer control status register, low part (TMCSR0, TMCSR1: L) .........................................258
Figure 11.4-4
16-bit timer register (TMR0, TMR1) ....................................................................................260
Figure 11.4-5
16-bit reload register (TMRLR0, TMRLR1) .........................................................................261
Figure 11.6-1
Internal clock mode setting ..................................................................................................264