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參數(shù)資料
| 型號(hào)： | MB86960APF-G |
| 廠商： | Fujitsu Limited |
| 英文描述： | NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE) |
| 中文描述： | 網(wǎng)絡(luò)接口控制器的編碼/解碼器（尼斯） |
| 文件頁數(shù)： | 46/65頁 |
| 文件大?。?/td> | 488K |
| 代理商： | MB86960APF-G |
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MB86960
t
1
t
3
t
2
t
5
t
4
t
6
t
9
t
8
t
7
SA0-3
CS
RD
RDY
RDY
SD15-0
(to NICE)
Figure 17. Write Cycle
TRISTATE
TRISTATE
TRISTATE
TRISTATE
Table 22. Write Cycle
Symbol
Parameter Description
Min.
Max.
Units
t
1
CS low to WE low; SA3–0 valid to WE low
3
ns
t
2
WE high to CS high; WE high to SA3–0 invalid
3
ns
t
3
WE low pulse width
36
ns
t
4
WE low to RDY low
0
26
ns
t
5
WE low to RDY TRISTATE
[1]
175
ns
t
6
WE low to RDY low
[2]
0
175
ns
t
7
WE high to RDY TRISTATE
28
ns
t
8
SD15–0 valid to WE high (data setup)
5
ns
t
9
WE high to SD15–0 invalid (data hold)
6
ns
1. 0 ns maximum for registers, and for Buffer Memory Port when port is ready before the write cycle begins. For port access only, 175 ns
maximum may occur if system makes contiguous system write cycles at less than 100 ns intervals, and both the transmitter and receiver
are active in “l(fā)oopback” reception.
2. 28 ns maximum for all registers. For port access only, 175 ns maximum may occur if system makes contiguous system write cycles at
less than 100 ns intervals, and both the transmitter and receiver are active in “l(fā)oopback” reception.
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| MB86961A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET |
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| MB86961APF-G | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET |
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| MB86965B | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
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