
FUJISTU LIMITED PRELIMINARY AN D CONFIDENTIAL
MB86295S<Coral-LP>
36
Specification Manual Rev1.1
The figure below illustrates a PCI to Coral (Master Read) transfer. The Host CPU will program up the
BCU registers (using normal PCI Slave writes) and trigger the transfer. The Coral then reads data from
the source memory as a PCI Master and writes to the destination inside the Coral.
All other BCU transfers use the BCU RAM in a similar way but with source/destination dependent on
transfer type.
3.2.2
Burst Controller Control/Status
All setup/control and status for the burst controller can be done through registers. These provide ways
of specifying the parameters for a burst (source/destination address, address increment (or not) and
burst/transfer size. In addition, a transfer can be started/paused/aborted and also its progress
monitored using the enable and status registers.
The key status indicators are Burst Complete and Transfer Complete, which become active at the end
of each burst/transfer respectively. These may either be active high or toggle state at the end of each
burst/transfer. When active high they will have to be cleared after each burst/transfer. This may be
done using a clear on read mode (default) or by manually writing to the appropriate register.
The burst/transfer complete indications are also available though the main interrupt status register
(IST) and can trigger the main external interrupt (XINT). If being used for this they must be configured
as active high (ie. not toggle mode). In addition burst/transfer complete can be made available as
external signals (BC/TC) for connection directly to an external device (eg. through some form of GPIO
or interrupt).
Normally a transfer will be configured and enabled using internal registers. However it is possible to
configure the transfer but not actually start it. An external signal (BEN) can then be used to trigger the
transfer and pause it between bursts. This may be useful, for example, when doing PCI Master reads
from a client which takes time to pre-fetch more data for the next burst.
Coral LP
Host CPU
(PCI Master)
Memory
(PCI Slave)
BCU
RAM
1) Slave Write to
setup transfer
2) Master Read
from source
3) Onward transfer
to destination
PCI Bus
Internal Bus