參數(shù)資料
型號： MB8117405A-60
廠商： Fujitsu Limited
英文描述： CMOS 4M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4M ×4 位超級頁面存取模式動態(tài)RAM)
中文描述： 的CMOS 4米× 4位超頁模式動態(tài)RAM的CMOS（4米× 4位超級頁面存取模式動態(tài)內(nèi)存）
文件頁數(shù)： 23/28頁
文件大?。?/td> 348K
代理商： MB8117405A-60
23
MB8117405A-60/MB8117405A-70
HIGH-Z
HIGH-Z
ROW ADDRESS
“H” or “L”
CAS
CAS
Fig. 16 – RAS-ONLY REFRESH (WE = OE = “H” or “L”)
Fig. 17 – CAS-BEFORE-RAS REFRESH (ADRESS = WE = OE = “H” or “L”)
V
IH
V
IL
RAS
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
A
0
to A
10
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
RAS
DQ
(Output)
DESCRIPTION
Refresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 2048 row
addresses every 32.8-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden
refresh.
RAS-only refresh is performed by keeping RAS Low and CAS High throughout the cycle; the row address to be refreshed is latched
on the falling edge of RAS. During RAS-only refresh, D
OUT
pin is kept in a high-impedance state.
DESCRIPTION
CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If CAS is held Low
for the specified setup time (t
CSR
) before RAS goes Low, the on-chip refresh control clock generators and refresh address counter
are enabled. An internal refresh operation automatically occurs and the refresh address counter is internally incremented in prep-
aration for the next CAS-before-RAS refresh operation.
DQ
(Output)
t
RAS
t
RC
t
RP
t
RPC
t
CRP
t
RAH
t
ASR
t
CRP
t
OFF
t
OH
t
RC
t
RP
t
RAS
t
CPN
t
CSR
t
CHR
t
RPC
t
CSR
t
CPN
t
OFF
t
OH
相關(guān)PDF資料
PDF描述
MB8117405A-70 CMOS 4M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4M ×4 位超級頁面存取模式動態(tài)RAM)
MB8117405B-50 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁面存取模式RAM)
MB8117405B-60 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁面存取模式RAM)
MB8117800A-70 CMOS 2 M ×8BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁面存取模式動態(tài)RAM)
MB8117800A-60 CMOS 2 M ×8BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁面存取模式動態(tài)RAM)
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參數(shù)描述
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