參數(shù)資料
型號(hào)： MB8117405B-50
廠商： Fujitsu Limited
英文描述： 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁(yè)面存取模式RAM)
中文描述： 4米× 4位快速頁(yè)面模式動(dòng)態(tài)RAM（的CMOS 4米× 4位快速頁(yè)面存取模式的RAM）
文件頁(yè)數(shù)： 1/31頁(yè)
文件大?。?/td> 588K
代理商： MB8117405B-50
1
DS05-
11318
-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS
4 M
HYPER PAGE MODE DYNAMIC RAM
MB8117405B-50/-60
×
4 BIT
CMOS 4,194,304
×
4 BIT Hyper Page Mode Dynamic RAM
I
DESCRIPTION
The Fujitsu MB8117405B is a fully decoded CMOS Dynamic RAM (DRAM) that contains 16,777,216 memory
cells accessible in 4-bit increments. The MB8117405B features a “hyper page” mode of operation whereby high-
speed random access of up to 1,024-bits of data within the same row can be selected. The MB8117405B DRAM
is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory
applications where very low power dissipation and high bandwidth are basic requirements of the design. Since
the standby current of the MB8117405B is very small, the device can be used as a non-volatile memory in
equipment that uses batteries for primary and/or auxiliary power.
The MB8117405B is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon and two-
layer aluminum process. This process, coupled with advanced stacked capacitor memory cells, reduces the
possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for
the MB8117405B are not critical and all inputs are TTL compatible.
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PRODUCT LINE & FEATURES
Parameter
MB8117405B-50
50 ns max.
84 ns min.
25 ns max.
15 ns max.
20 ns min.
660 mW max.
11 mW max. (TTL level)/5.5 mW max. (CMOS level)
MB8117405B-60
60 ns max.
104 ns min.
30 ns max.
15 ns max.
25 ns min.
550 mW max.
RAS Access Time
Randam Cycle Time
Address Access Time
CAS Access Time
Hyper Page Mode Cycle Time
Low Power
Dissipation
Operating Current
Standby Current
4,194,304 words
×
4 bits organization
Silicon gate, CMOS, Advanced Capacitor Cell
All input and output are TTL compatible
2048 refresh cycles every 32.8 ms
Early Write or OE controlled write capability
RAS only, CAS-before-RAS, or Hidden
Refresh
Hyper Page Mode, Read-Modify-Write
capability
On chip substrate bias generator for high
performance
相關(guān)PDF資料
PDF描述
MB8117405B-60 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁(yè)面存取模式RAM)
MB8117800A-70 CMOS 2 M ×8BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
MB8117800A-60 CMOS 2 M ×8BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
MB8117805A-60 CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB8117805A-70 CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB8117800A-60 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM
MB8117800A-70 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM
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