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參數(shù)資料
| 型號： | MB8117405B-50 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁面存取模式RAM) |
| 中文描述： | 4米× 4位快速頁面模式動態(tài)RAM（的CMOS 4米× 4位快速頁面存取模式的RAM） |
| 文件頁數(shù)： | 5/31頁 |
| 文件大?。?/td> | 588K |
| 代理商： | MB8117405B-50 |
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MB8117405B-50/-60
I
FUNCTIONAL TRUTH TABLE
X: “H” or “L”
*: It is impossible in Hyper Page Mode
I
FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty-two input bits are required to decode any four of 16,777,216 cell addresses in the memory matrix. Since
only twelve address bits (A
0
to A
10
) are available, the row and column inputs are separately strobed by RAS and
CAS as shown in Figure 1. First, twelve row address bits are input on pins A
row address strobe (RAS) then, ten column address bits are input and latched with the column address strobe
(CAS). Both row and column addresses must be stable on or before the falling edge of RAS and CAS, respectively.
The address latches are of the flow-through type; thus, address information appearing after t
automatically treated as the column address.
0
-through-A
10
and latched with the
RAH
(min.)+ t
T
is
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated;
when WE is High, a read cycle is selected. During the read mode, input data is ignored.
DATA INPUTS
Input data is written into memory in either of three basic ways : an early write cycle, an OE (delayed) write cycle,
and a read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch
strobe. In an early write cycle, the input data (DQ
1
to DQ
referenced to CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE goes
Low after CAS ; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable
signal.
4
) is strobed by CAS and the setup/hold times are
Operation Mode
Clock Input
Address Input
Input Data
Refresh
Note
RAS
CAS
WE
OE
Row
Column
Input
Output
Standby
H
H
X
X
—
—
—
High-Z
—
Read Cycle
L
L
H
L
Valid
Valid
—
Valid
Yes *
t
RCS
≥
t
RCS
(min)
Write Cycle
(Early Write)
L
L
L
X
Valid
Valid
Valid
High-Z
Yes *
t
WCS
≥
t
WCS
(min)
Read-Modify-
Write Cycle
L
L
H
→
L
L
→
H
Valid
Valid
Valid
Valid
Yes *
RAS-only
Refresh Cycle
L
H
X
X
Valid
—
—
High-Z
Yes
CAS-before-
RAS Refresh
Cycle
L
L
H
X
—
—
—
High-Z
Yes
t
CSR
≥
t
CSR
(min)
Hidden Refresh
Cycle
H
→
L
L
H
→
X
L
—
—
—
Valid
Yes
Previous data is
kept.
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