參數(shù)資料
型號： MB8116405A-60
廠商： Fujitsu Limited
英文描述： CMOS 4M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4M ×4 位超級頁面存取模式動態(tài)RAM)
中文描述： 的CMOS 4米× 4位超頁模式動態(tài)RAM的CMOS（4米× 4位超級頁面存取模式動態(tài)內(nèi)存）
文件頁數(shù)： 18/28頁
文件大?。?/td> 536K
代理商： MB8116405A-60
18
MB8116405A-60/MB8116405A-70
Fig. 10 – HYPER PAGE MODE READ CYCLE (WE Control)
V
IH
V
IL
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
CAS
A
0
to A
11
WE
DQ
(Input)
DQ
(Output)
“H” or “L”
DESCRIPTION
The hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address.
This operation is performed by strobing in the row address and maintaining RAS at a Low level during all successive memory cycles in
which the row address is latched. The access time is determined by t
CAC
, t
AA
, t
CPA
, or t
OEA
, whichever one is the latest in occurring.
To obtain a high impedance state, confirm either of the following conditions, OE set to a High level or WE set to a Low level after CAS set
to a High level or RAS and CAS set to a High level.
V
IH
V
IL
OE
t
t
CRP
t
ASR
t
ASC
t
RCS
t
RHCP
t
RP
ROW
COL
ADD
t
CAS
t
RSH
t
HPC
t
CAS
t
CAS
t
DZC
t
CAH
t
CAH
t
ASC
t
ASC
t
RCH
t
CAC
t
AA
t
CSH
t
RAL
HIGH-Z
t
OFF
t
OH
t
OEZ
t
RDD
t
OFR
t
OH
t
OH
t
AA
t
CAC
t
ON
t
AA
t
OEA
t
DZO
t
ON
t
RAC
t
RCS
t
RCH
t
WPZ
t
RCH
t
CAL
t
WEZ
t
ON
t
WEZ
t
WPZ
t
CDD
t
WED
t
WEZ
t
ON
t
AR
t
RCS
COL
ADD
t
WPZ
t
RCD
COL
ADD
t
CAC
t
OED
t
RAH
t
RAD
VALID
VALID
VALID
HIGH-Z
t
CAH
During one cycle is achieved in hyper-page mode, the input/output timing apply the same manner
as the former cycle.
相關(guān)PDF資料
PDF描述
MB8116405A-70 CMOS 4M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4M ×4 位超級頁面存取模式動態(tài)RAM)
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