參數(shù)資料
型號： MB8116405A-60
廠商： Fujitsu Limited
英文描述： CMOS 4M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4M ×4 位超級頁面存取模式動態(tài)RAM)
中文描述： 的CMOS 4米× 4位超頁模式動態(tài)RAM的CMOS（4米× 4位超級頁面存取模式動態(tài)內(nèi)存）
文件頁數(shù)： 10/28頁
文件大?。?/td> 536K
代理商： MB8116405A-60
10
MB8116405A-60/MB8116405A-70
Notes: 1. Referenced to V
SS
.
2. I
CC
depends on the output load conditions and cycle rates; The specified values are obtained with the
output open. I
CC
depends on the number of address change as RAS = V
IL
, CAS = V
IH
and V
IL
> –0.3 V.
I
CC1
, I
CC3
, I
CC4
and I
CC5
are specified at one time of address change during RAS = V
IL
and CAS = V
IH
.
I
CC2
is specified during RAS = V
IH
and V
IL
> –0.3 V.
3. An initial pause (RAS = CAS = V
IH
) of 200
μ
s is required after power-up followed by any eight RAS-
only cycles before proper device operation is achieved. In case of using internal refresh counter, a
minimum of eight CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
4. AC characteristics assume t
T
= 2 ns.
5. V
IH
(min.) and V
IL
(max.) are reference levels for measuring timing of input signals. Also transition times
are measured between V
IH
(min.) and V
IL
(max.).
6. Assumes that t
RCD
≤
t
RCD
(max.), t
RAD
≤
t
RAD
(max.). If t
RCD
is greater than the maximum recommended
value shown in this table, t
RAC
will be increased by the amount that t
RCD
exceeds the value shown. Refer
to Fig. 2 and 3.
7. If t
RCD
≥
t
RCD
(max.), t
RAD
≥
t
RAD
(max.), and t
ASC
≥
t
AA
– t
CAC
– t
T
, access time is t
CAC
.
8. If t
RAD
≥
t
RAD
(max.) and t
ASC
≤
t
AA
– t
CAC
– t
T
, access time is t
AA
.
9. Measured with a load equivalent to two TTL loads and 50 pF.
10. t
OFF
and t
OEZ
is specified that output buffer change to high impedance state.
11. Operation within the t
RCD
(max.) limit ensures that t
RAC
(max.) can be met. t
RCD
(max.) is specified as a
reference point only; if t
RCD
is greater than the specified t
RCD
(max.) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
12. t
RAD
(min.) = t
RAH
(min.) + 2 t
T
+ t
ASC
(min.).
13. Operation within the t
RAD
(max.) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.) is specified as
a reference point only; if t
RAD
is greater than the specified t
RAD
(max.) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
14. Either t
RRH
or t
RCH
must be satisfied for a read cycle.
15. t
WCS
is specified as a reference point only. If t
WCS
≥
t
WCS
(min.) the data output pin will remain High-Z
state through entire cycle.
16. Assumes that t
WCS
< t
WCS
(min.).
17. Either t
DZC
or t
DZO
must be satisfied.
18. t
CPA
is access time from the selection of a new column address (that is caused by changing CAS from
“L” to “H”). Therefore, if t
OP
is long, t
OPA
is longer than t
OPA
(max.).
19. Assumes that CAS-before-RAS refresh.
20. t
WCS
, t
CWD
, t
RWD
and t
AWD
are not restrictive operating parameters. They are included in the data sheet
as an electrical characteristic only. If t
WCS
> t
WCS
(min.), the cycle is an early write cycle and Dout pin
will maintain high impedance state thoughout the entire cycle. If t
CWD
> t
CWD
(min.), t
RWD
> t
RWD
(min.),
and t
AWD
> t
AWD
(min.), the cycle is a read modify-write cycle and data from the selected cell will appear
at the Dout pin. If neither of the above conditions is satisfied, the cycle is a delayed write cycle and
invalid data will appear the Dout pin , and write operation can be executed by satisfying t
RWL
, t
CWL
, and
t
RAL
specifications.
21. The last CAS rising edge.
22. The first CAS falling edge.
相關PDF資料
PDF描述
MB8116405A-70 CMOS 4M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4M ×4 位超級頁面存取模式動態(tài)RAM)
MB81164442A-100L CMOS 4×4M×16 BIT Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4×4M×16 位同步動態(tài)RAM)
MB81164442A-100 CMOS 4×4M×16 BIT Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4×4M×16 位同步動態(tài)RAM)
MB81164442A-125 CMOS 4×4M×16 BIT Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4×4M×16 位同步動態(tài)RAM)
MB81164442A-125L CMOS 4×4M×16 BIT Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4×4M×16 位同步動態(tài)RAM)
相關代理商/技術參數(shù)
參數(shù)描述
MB8116E 制造商:FUJITSU 功能描述: 制造商:FUJITSU 功能描述:8116E
MB8117800A-60 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM
MB8117800A-70 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM
MB812 功能描述:ACCY MOUNT BMM 3/4 58A RoHS:是 類別:RF/IF 和 RFID >> RF配件 系列:* 標準包裝:1 系列:*
MB812.833 功能描述:ACCY MOUNT BMM 3/4 58A RoHS:是 類別:RF/IF 和 RFID >> RF配件 系列:* 標準包裝:1 系列:*
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*