參數(shù)資料
型號(hào)： MB81164442A-100L
廠商： Fujitsu Limited
英文描述： CMOS 4×4M×16 BIT Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4×4M×16 位同步動(dòng)態(tài)RAM)
中文描述： 的CMOS 4 × 4米× 16位同步動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器（SDRAM）（的CMOS 4 × 4米× 16位同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 1/46頁(yè)
文件大?。?/td> 642K
代理商： MB81164442A-100L
1
DS05-11025-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS
4
×
4 M
SYNCHRONOUS DYNAMIC RAM
×
4 BIT
MB81164442A-125/-100/-84/-67/-125L/-100L/-84L/-67L
CMOS 4-BANK
Synchronous Dynamic Random Access Memory
×
4,194,304-WORD
×
4 BIT
I
DESCRIPTION
The Fujitsu MB81164442A is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
67,108,864 memory cells accessible in a 4-bit format. The MB81164442A features a fully synchronous operation
referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high
performance and simple user interface coexistence. The MB81164442A SDRAM is designed to reduce the
complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing constraints,
and may improve data bandwidth of memory as much as 5 times more than a standard DRAM.
The MB81164442A is ideally suited for workstations, personal computers, laser printers, high resolution graphic
adapters/accelerators and other applications where an extremely large memory and bandwidth are required and
where a simple interface is needed.
I
PRODUCT LINE & FEATURES
Parameter
MB81164442A
-100/-100L
100 MHz max.
10 ns min.
54 ns max.
24 ns max.
8.5 ns max.
140 mA max.
3 mA max. (std power)
1 mA max. (low power)
2 mA max. (std power)
500
μ
A max. (low power)
-125/-125L
125 MHz max.
8 ns min.
45 ns max.
21 ns max.
7.5 ns max.
160 mA max.
-84/-84L
84 MHz max.
12 ns min.
56 ns max.
26 ns max.
8.5 ns max.
130 mA max.
-67/-67L
67 MHz max.
15 ns min.
60 ns max.
30 ns max.
9 ns max.
120 mA max.
Clock Frequency
Burst Mode Cycle Time
RAS Access Time
CAS Access Time
Access Time From Clock (CL = 3)
Operating Current (2 banks active)
Power Down Mode Current (I
CC2P
)
Self Refresh Current (I
CC6
)
Single +3.3 V Supply
±
0.3 V tolerance
LVTTL compatible I/O
4 K refresh cycles every 65.6 ms
Four bank operation
Burst read/write operation and burst
read/single write operation capability
Standard and low power versions
Programmable burst type, burst length, and
CAS latency
Auto-and Self-refresh (every 16
μ
s)
CKE power down mode
Output Enable and Input Data Mask
相關(guān)PDF資料
PDF描述
MB81164442A-100 CMOS 4×4M×16 BIT Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4×4M×16 位同步動(dòng)態(tài)RAM)
MB81164442A-125 CMOS 4×4M×16 BIT Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4×4M×16 位同步動(dòng)態(tài)RAM)
MB81164442A-125L CMOS 4×4M×16 BIT Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4×4M×16 位同步動(dòng)態(tài)RAM)
MB81164442A-67 CMOS 4×4M×16 BIT Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4×4M×16 位同步動(dòng)態(tài)RAM)
MB81164442A-67L CMOS 4×4M×16 BIT Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4×4M×16 位同步動(dòng)態(tài)RAM)
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