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| 型號： | MB81164442A-100L |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 4×4M×16 BIT Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4×4M×16 位同步動態(tài)RAM) |
| 中文描述： | 的CMOS 4 × 4米× 16位同步動態(tài)隨機(jī)存取存儲器（SDRAM）（的CMOS 4 × 4米× 16位同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 16/46頁 |
| 文件大小： | 642K |
| 代理商： | MB81164442A-100L |
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MB81164442A-125/-100/-84/-67/-125L/-100L/-84L/-67L
I
FUNCTIONAL DESCRIPTION
SDRAM BASIC FUNCTION
Three major differences between this SDRAM and conventional DRAMs are: synchronized operation, burst mode,
and mode register.
The
synchronized operation
is the fundamental difference. An SDRAM uses a clock input for the synchronization,
where the DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS. Each
operation of DRAM is determined by their timing phase differences while each operation of SDRAM is determined
by commands and all operations are referenced to a positive clock edge. Fig 3 shows the basic timing diagram
differences between SDRAMs and DRAMs.
The
burst mode
is a very high speed access mode utilizing an internal column address generator. Once a column
addresses for the first access is set, following addresses are automatically generated by the internal column address
counter.
The
mode registe
r is to justify the SDRAM operation and function into desired system conditions. MODE REGISTER
TABLE shows how SDRAM can be configured for system requirement by mode register programming.
CLOCK (CLK) and CLOCK ENABLE (CKE)
All input and output signals of SDRAM use register type buffers. A CLK is used as a trigger for the register and
internal burst counter increment. All inputs are latched by a positive edge of CLK. All outputs are validated by the
CLK. CKE is a high active clock enable signal. When CKE = Low is latched at a clock input during active cycle, the
next clock will be internally masked. During idle state (all banks have been precharged), the Power Down mode
(standby) is entered with CKE = Low and this will make extremely low standby current.
CHIP SELECT (CS)
CS enables all commands inputs, RAS, CAS, and WE, and address input. When CS is High, command signals are
negated but internal operation such as burst cycle will not be suspended. If such a control isn’t needed, CS can be
tied to ground level.
COMMAND INPUT (RAS, CAS and WE)
Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDRAM operation, such as Row address
strobe by RAS. Instead, each combination of RAS, CAS, and WE input in conjunction with CS input at a rising edge
of the CLK determines SDRAM operation. Refer to FUNCTIONAL TRUTH TABLE in page 5.
ADDRESS INPUT (A
0
to A
11
)
Address input selects an arbitrary location of a total of 4,194,304 words of each memory cell matrix. A total of
fourteen address input signals are required to decode such a matrix. SDRAM adopts an address multiplexer in
order to reduce the pin count of the address line. At a Bank Active command (ACTV), twelve Row addresses are
initially latched and the remainder of ten Column addresses are then latched by a Column address strobe command
of either a Read command (READ or READA) or Write command (WRIT or WRITA).
BANK SELECT (A
13
, A
12
)
This SDRAM has four banks and each bank is organized as 4 M words by 4-bit.
Bank selection by A
13
, A
12
occurs at Bank Active command (ACTV) followed by read (READ or READA), write (WRIT
or WRITA), and precharge command (PRE).
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