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參數(shù)資料
| 型號： | MACH1 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Performance EE CMOS Programmable Logic |
| 中文描述： | 高性能電子工程CMOS可編程邏輯 |
| 文件頁數(shù)： | 34/48頁 |
| 文件大?。?/td> | 1136K |
| 代理商： | MACH1 |
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4
MACH 1 & 2 Families
FUNCTIONAL DESCRIPTION
Each MACH 1 and 2 device consists of multiple, optimized PAL blocks interconnected by a switch
matrix. The switch matrix allows communication between PAL blocks, and routes inputs to the PAL
blocks. Together, the PAL blocks and switch matrix allow the logic designer to create large designs
in a single device instead of using multiple devices.
The switch matrix takes all dedicated inputs and signals from the input switch matrices and routes
them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must
go through the switch matrix. This mechanism ensures that PAL blocks in MACH devices
communicate with each other with guaranteed xed timing (SpeedLocking).
The switch matrix makes a MACH device more advanced than simply several PAL devices on a
single chip. It allows the designer to think of the device not as a collection of blocks, but as a
single programmable device; the software partitions the design into PAL blocks through the
central switch matrix so that the designer does not have to be concerned with the internal
architecture of the device.
14051K-002
Figure 1. Overall Architecture of MACH 1 & 2 Devices
Array and
Allocator
Output
Macrocells
Buried
Macrocells
I/O Cells
Buried Macrocell Feedback
Output Macrocell Feedback
I/O Pin Feedback
I/O Pins
Switch
Matrix
PAL Block
I/O Pins
PAL Block
Clock/Input Pins
Dedicated Input
Note:
1. There are no buried macrocells in MACH 1 devices. All macrocells are output macrocells.
PAL Block
Device
PAL Blocks
Macrocells per Block
I/Os per Block
Product Terms per Block
MACH111(SP)
21616
70
MACH131(SP)
41616
70
MACH211(SP)
416
8
68
MACH221(SP)
812
6
52
MACH231(SP)
816
8
68
(note 1)
I/O Pins
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MACH210A-10JC | High-Density EE CMOS Programmable Logic |
| MACH210A-10VC | High-Density EE CMOS Programmable Logic |
| MACH210A-12JC | High-Density EE CMOS Programmable Logic |
| MACH210A-12VC | High-Density EE CMOS Programmable Logic |
| MACH210A-7 | High-Density EE CMOS Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MACH10015JC | 制造商:AMD 功能描述:NEW |
| MACH102-24TP-F | 制造商:HIRSCHMANN INDUSTRIAL 功能描述:ETHERNET SWITCH, 19 IN. RACK MOUNT, 24 PORTS 10/100BASETX, 2 GIG COMBO PORTS |
| MACH102-24TP-FR | 制造商:HIRSCHMANN INDUSTRIAL 功能描述:ETHERNET SWITCH, 19 IN. RACK MOUNT SWITCH, 24 PORTS 10/100BASETX, 2 COMBO PORTS |
| MACH102-8TP | 制造商:HIRSCHMANN INDUSTRIAL 功能描述:ETHERNET SWITCH, 19 IN. RACK MOUNT, 8 PORTS 10/100BASETX, 2 COMBO PORTS |
| MACH102-8TP-F | 制造商:HIRSCHMANN INDUSTRIAL 功能描述:ETHERNET SWITCH, 19 IN. RACK MOUNT, 8 PORTS 10/100BASETX, 2 GIG COMBO PORTS |
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