參數(shù)資料
型號(hào)： MACH1
廠商： Lattice Semiconductor Corporation
英文描述： High-Performance EE CMOS Programmable Logic
中文描述： 高性能電子工程CMOS可編程邏輯
文件頁(yè)數(shù)： 3/48頁(yè)
文件大小： 1136K
代理商： MACH1
MACH 1 & 2 Families
11
The ip-ops in either macrocell type can be clocked by one of several clock pins (Table 10).
Registers are clocked on the rising edge of the clock input. Latches hold their data when the gate
input is HIGH. Clock pins are also available as inputs, although care must be taken when a signal
acts as both clock and input to the same device.
All ip-ops have asynchronous reset and preset. This is controlled by the common product terms
that control all ip-ops within a PAL block. For a single PAL block, all ip-ops, whether in an
output or a buried macrocell, are initialized together. The initialization functionality of the ip-ops
is illustrated in Table 11.
I/O Cells
The I/O cells (Figure 7) provide a three-state output buffer. The three-state buffer can be left
permanently enabled for use only as an output, permanently disabled for use as an input, or it can
be controlled by one of two product terms for bi-directional signals and bus connections. The two
product terms provided are common to a bank of I/O cells.
Table 10. Macrocell Clocks
Device
Number of Clocks Available
Device
Number of Clocks Available
MACH111
4
MACH211SP
2
MACH111SP
2
MACH221
4
MACH131
4
MACH221SP
4
MACH131SP
4
MACH231
4
MACH211
4
MACH231SP
4
Table 11. Asynchronous Reset/Preset Operation
Conguration
AR
AP
CLK/LE
Q+
Register
0
X
See Table 9
01
X
1
10
X
0
11
X
0
Latch
0
X
See Table 9
0
1
0
Illegal
01
1
0
Illegal
10
1
0
1
0
Illegal
11
1
0
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