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參數(shù)資料
| 型號： | MACH1 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Performance EE CMOS Programmable Logic |
| 中文描述： | 高性能電子工程CMOS可編程邏輯 |
| 文件頁數(shù)： | 20/48頁 |
| 文件大小： | 1136K |
| 代理商： | MACH1 |
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MACH 1 & 2 Families
27
MACH211 AND MACH211SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES
1
Parameter
Symbol
Parameter Description
-6
-7
-10
-12
-14
-15
-18
Unit
Min Max
Min
Max
Min
Max
Min Max Min Max Min Max Min
Max
tPD
Input, I/O, or Feedback to Combinatorial
Output
6
7.5
10
12
14
15
18
ns
tS
Setup Time from Input, I/O, or Feedback
to Clock
D-type
5
5.5
6.5
7
8.5
10
12
ns
T-type
5.5
6.5
7.5
8
10
11
13.5
ns
tH
Register Data Hold Time
0
0000
ns
tCO
Clock to Output
4
4.5
6
8
10
12
ns
tWL
Clock Width
LOW
2.5
3
5
6
7.5
ns
tWH
HIGH
2.5
3
5
6
7.5
ns
fMAX
Maximum
Frequency
External
Feedback
1/(tS + tCO)
D-type
111
100
80
66.7
54
50
42
MHz
T-type
105
91
74
62.5
50
47.6
39
MHz
Internal Feedback (fCNT)
D-type
166
133
100
83.3
69
66.6
55.6
MHz
T-type
150
125
91
76.9
62.5
51.3
MHz
No Feedback 1/(tWL + tWH)
200
167
100
83.3
66.7
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate
5
5.5
6.5
7
8.5
10
12
ns
tHL
Latch Data Hold Time
0
0000
ns
tGO
Gate to Output
7
7.5
(note 4)
7
8
(note 5)
10
11
13
(note 6)
13.5
ns
tGWL
Gate Width LOW
2.5
3
5
6
7.5
ns
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
9
9.5
12
14
17
20
(note 6)
20.5
ns
tSIR
Input Register Setup Time
1.5
2
2.5
ns
tHIR
Input Register Hold Time
1.5
2
2.5
3.5
ns
tICO
Input Register Clock to Combinatorial Output
10
11
13
15
18
20
(note 6)
22
ns
tICS
Input Register Clock to Output Register
Setup
D-type
8
9
10
12
14.5
15
18
ns
T-type
9
10
11
13
16
19.5
ns
tWICL
Input Register
Clock Width
LOW
2.5
3
5
6
7.5
ns
tWICH
HIGH
2.5
3
5
6
7.5
ns
fMAXIR
Maximum Input Register
Frequency
1/(tWICL + tWICH)
200
167
100
83.3
66.7
MHz
tSIL
Input Latch Setup Time
1.5
2
2.5
ns
tHIL
Input Latch Hold Time
1.5
2
2.5
3.5
ns
tIGO
Input Latch Gate to Combinatorial Output
12
14
17
20
24
ns
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
13
14
16
19
22
26.5
ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
7
7.5
8.5
9
11
12
14.5
ns
tIGS
Input Latch Gate to Output Latch Setup
9
10
11
13
16
19.5
ns
tWIGL
Input Latch Gate Width LOW
2.5
3
5
6
7.5
ns
tPDLL
Input, I/O, or Feedback to Output Through
Transparent Input and Output Latches
12
12.5
14
16
19
23
ns
相關PDF資料 |
PDF描述 |
|---|---|
| MACH210A-10JC | High-Density EE CMOS Programmable Logic |
| MACH210A-10VC | High-Density EE CMOS Programmable Logic |
| MACH210A-12JC | High-Density EE CMOS Programmable Logic |
| MACH210A-12VC | High-Density EE CMOS Programmable Logic |
| MACH210A-7 | High-Density EE CMOS Programmable Logic |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MACH10015JC | 制造商:AMD 功能描述:NEW |
| MACH102-24TP-F | 制造商:HIRSCHMANN INDUSTRIAL 功能描述:ETHERNET SWITCH, 19 IN. RACK MOUNT, 24 PORTS 10/100BASETX, 2 GIG COMBO PORTS |
| MACH102-24TP-FR | 制造商:HIRSCHMANN INDUSTRIAL 功能描述:ETHERNET SWITCH, 19 IN. RACK MOUNT SWITCH, 24 PORTS 10/100BASETX, 2 COMBO PORTS |
| MACH102-8TP | 制造商:HIRSCHMANN INDUSTRIAL 功能描述:ETHERNET SWITCH, 19 IN. RACK MOUNT, 8 PORTS 10/100BASETX, 2 COMBO PORTS |
| MACH102-8TP-F | 制造商:HIRSCHMANN INDUSTRIAL 功能描述:ETHERNET SWITCH, 19 IN. RACK MOUNT, 8 PORTS 10/100BASETX, 2 GIG COMBO PORTS |
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