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參數(shù)資料
| 型號(hào)： | M5M4V4S40CTP-15 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| 中文描述： | 4分（2 -銀行甲131072字x 16位）同步DRAM |
| 文件頁(yè)數(shù)： | 29/45頁(yè) |
| 文件大小： | 1458K |
| 代理商： | M5M4V4S40CTP-15 |
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29
M5M4V4S40CTP-12, -15
Feb ‘97
Preliminary
MITSUBISHI LSIs
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 0.3)
AC TIMING REQUIREMENTS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Input Pulse Levels : 0.8V to 2.0V
Input Timing Measurement Level : 1.4V
Symbol Parameter
Limits
Unit
-12
-15
Min.
Max.
Min.
Max.
tCLK
CLK cycle time
CL=1
30
30
ns
CL=2
15
15
ns
CL=3
12
15
ns
tCH
CLK High pulse width
4
4
ns
tCL
CLK Low pulse width
4
4
ns
tT
Transition time of CLK
1
10
1
10
ns
tIS
Input Setup time (all inputs)
3
3
ns
tIH
Input Hold time (all inputs)
1
1.5
ns
tRC
Row Cycle time
100
120
ns
tRCD
Row to Column Delay
30
30
ns
tRAS
Row Active time
70
10000
75
10000
ns
tRP
Row Precharge time
30
40
ns
tWR
Write Recovery time
12
15
ns
tRRD
Act to Act Delay time
24
30
ns
tRSC
Mode Register Set
Cycle time
24
30
ns
tPDE
Power Down Exit time
12
15
ns
tREF
Refresh Interval time
16.4
16.4
ms
CLK
Signal
1.4V
1.4V
Any AC timing is
referenced to the input
signal passing through
1.4V.
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| M5M4V64S20ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
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| M5M4V64S20ATP-8A | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
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