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參數(shù)資料
| 型號： | M5M4V4S40CTP-15 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| 中文描述： | 4分（2 -銀行甲131072字x 16位）同步DRAM |
| 文件頁數(shù)： | 24/45頁 |
| 文件大?。?/td> | 1458K |
| 代理商： | M5M4V4S40CTP-15 |
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M5M4V4S40CTP-12, -15
Feb ‘97
Preliminary
MITSUBISHI LSIs
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 0.3)
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L).
Once initiated, the self-refresh is maintained as long as CKE is kept low. During the self-refresh mode,
CKE is asynchronous and all other inputs including CLK are disabled and ignored. Disabling all inputs
except CKE during self-refresh reduces power consumption. To exit the self-refresh, supply a stable CLK
input, issue a DESEL or NOP command, and set CKE=H (REFSX). After tRC from REFSX both banks
will be in the idle state new commands can be issued. Until the tRC time has expired, only DESELor NOP
commands may be asserted after an REFSX command.
Self-Refresh
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-8
BA
Self Refresh Entry
Self Refresh Exit
X
0
minimum tRC
for recovery
Stable CLK
NOP
new command
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| M5M4V64S20ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-10L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8A | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
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