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參數(shù)資料
| 型號： | M5M4V4S40CTP-15 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| 中文描述： | 4分（2 -銀行甲131072字x 16位）同步DRAM |
| 文件頁數(shù)： | 18/45頁 |
| 文件大?。?/td> | 1458K |
| 代理商： | M5M4V4S40CTP-15 |
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M5M4V4S40CTP-12, -15
Feb ‘97
Preliminary
MITSUBISHI LSIs
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 0.3)
BURST INTERRUPTION
[ Read Interrupted by Read ]
A burst read operation can be interrupted by a new read of the same or opposite bank. M5M4V4S40CTP
allows random column accesses. READ to READ interval is a minimum of one CLK.
[ Read Interrupted by Write ]
A burst read operation can be interrupted by a write to the same or opposite bank. For this operation,
the DQ’s should be controlled by using DQMU and DQML to prevent bus contention. The output is
disabled two cycles automatically after WRITE assertion. Random column access is allowed.
Read Interrupted by Read (BL=4, CL=3)
CLK
Command
A0-7
A8
BA
DQ
READ
Yi
0
0
READ
Yk
0
1
Qai0
Qaj1 Qbk0 Qbk1
READ
Yj
0
0
Qaj0
Qbk2
Qal0
READ
Yl
0
0
Qal1
Qal2
Qal3
Read Interrupted by Write (BL=4, CL=3)
CLK
Command
A0-7
A8
BA
Q
Qai0
D
Daj0
Daj1
Daj2
Daj3
DQMU
DQML
DQMU/DQML control
Write control
Read
Yi
0
0
Write
Yj
0
0
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| M5M4V64S20ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-10L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8A | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
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