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參數(shù)資料
| 型號： | M5M4V16169DRT-8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 22182053 |
| 中文描述： | 16MCDRAM：16米（100萬字由16位）與16K的緩存內(nèi)存（1024字由16位）的SRAM |
| 文件頁數(shù)： | 59/64頁 |
| 文件大?。?/td> | 737K |
| 代理商： | M5M4V16169DRT-8 |
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MITSUBISHI LSIs
(REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
2
3
4
5
6
7
8
9
10
11
12
13
14
1
RAS#
CAS#
DTD#
Ad0-2
Ad3-11
WB1
Old Data
**Col
CS#
Ad0-Ad2=Low
PCG
DPD DPD
DPD DPD
ACT
DWT1
PCG
DPD
DNOP
DNOP
DPD
BW
BW
BW
BW
BW
BW
BW
BW
BW
BW
BW
BW
BW
DQ0-15
tRP
tRCD
Row
Row
tRASP
tRWL
1
2
3
4
5
6
7
0
1
2
3
4
5
DRAM
SRAM
0
WB2
1
2
3
4
5
6
7
0
1
2
3
4
0
DES
DRAM Write Transfer2 & Read (WB2->DRAM->RB1-> RB2) Latency set=1
DWT2
DNOP
tPC
Ad2=Low
**Col
New
Data[WB1(0-7)]
Ad0,Ad1=High
NoChange
RB1
Old Data
New Data[WB1(0-7)]
Latency x t
K
tCBF
New Data on RB appears as to latency set count. See DRT timing chart.
59
RB1
Old Data
New Data[WB1(0-7)]
K
CMd#
SRAM operation can be freely performed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V16169DTP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
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