參數(shù)資料
型號： M59MR032D
廠商： 意法半導(dǎo)體
英文描述： 32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述： 32兆位的2Mb x16插槽，復(fù)用的I / O，雙行，突發(fā)1.8V電源快閃記憶體
文件頁數(shù)： 10/49頁
文件大?。?/td> 352K
代理商： M59MR032D
M59MR032C, M59MR032D
10/49
Table 8. User Bus Operations
(1)
Note: 1. X = Don’t care.
Table 9. Read Electronic Signature (AS and Read CFI instructions)
(1)
Note: 1. Addresses are latched on the rising edge of L input.
Table 10. Read Block Protection (AS and Read CFI instructions)
(1)
Note: 1. Addresses are latched on the rising edge of L input.
2. A locked block can be unprotected only with WP at V
IH.
Operation
E
G
W
RP
WP
ADQ0-ADQ15
Write
V
IL
V
IH
V
IL
V
IH
V
IH
Data Input
Output Disable
V
IL
V
IH
V
IH
V
IH
V
IH
Hi-Z
Standby
V
IH
X
X
V
IH
V
IH
Hi-Z
Reset / Power-down
X
X
X
V
IL
V
IH
Hi-Z
Block Locking
V
IL
X
X
V
IH
V
IL
X
Code
Device
E
G
W
A0-A7
A8-A20
Data
Manufacturer Code
V
IL
V
IL
V
IH
00h
Don’t Care
0020h
Device Code
M59MR032C
V
IL
V
IL
V
IH
01h
Don’t Care
00A4h
M59MR032D
V
IL
V
IL
V
IH
01h
Don’t Care
00A5h
Block Status
E
G
W
A0-A7
A8-A11
A12-A20
Data
Protected and
unlocked
V
IL
V
IL
V
IH
02h
Don’t Care
Block Address
0001
Unprotected and
unlocked
V
IL
V
IL
V
IH
02h
Don’t Care
Block Address
0000
Protected and locked
V
IL
V
IL
V
IH
02h
Don’t Care
Block Address
0003
Unprotected and
locked
(2)
V
IL
V
IL
V
IH
02h
Don’t Care
Block Address
0002
DEVICE OPERATIONS
The following operations can be performed using
the appropriate bus cycles: Address Latch, Read
Array (Random, and Page Modes), Write com-
mand, Output Disable, Standby, Reset/Power-
down and Block Locking. See Table 8.
Address Latch.
In asynchronous operation, the
address is latched on the rising edge of L input; in
burst mode, the address is latched either by L go-
ing high or with a rising/falling edge of K, depend-
ing on the clock configuration.
Read.
Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register, the CFI, the Block
Protection Status, the Configuration Register sta-
tus and the Security Code.
Read operation of the Memory Array may be per-
formed in asynchronous page mode or synchro-
nous burst mode. In asynchronous page mode
data is internally read and stored in a page buffer.
The page has a size of 4 words and is addressed
by ADQ0 and ADQ1 address inputs.
According to the device configuration the following
Read operations: Electronic Signature - Status
Register - CFI - Block Protection Status - Configu-
ration Register Status - Security Code must be ac-
cessed as asynchronous read or as single
synchronous burst mode (see Figure 4). Both Chip
Enable E and Output Enable G must be at V
IL
in
order to read the output of the memory.
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