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參數(shù)資料
| 型號(hào)： | M59BW102 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 1 Mbit 64Kb x16, Burst Low Voltage Flash Memory |
| 中文描述： | 1兆位64Kb的x16插槽，突發(fā)低電壓快閃記憶體 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 181K |
| 代理商： | M59BW102 |
M59BW102
6/24
Figure 4. Block Diagram
AI02765
ODD MATRIX
(16 x 32K)
EVEN MATRIX
(16 x 32K)
G
E
ALE
MULTIPLEXER
EVEN COUNTER
OUTPUT BUFFER
ODD COUNTER
DQ0-DQ15
A1-A15
LOGIC
A0
INSTRUCTIONS AND COMMANDS
The Command Interface latches commands writ-
ten to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, Read Electronic Signature, Program, Chip
Erase. Commands are made of address and data
sequences. The instructions require from 1 to 6 cy-
cles, the first or first three of which are always write
operations used to initiate the instruction. They are
followed by either further write cycles to confirm
the first command or execute the command imme-
diately. Command sequencing must be followed
exactly. Any invalid combination of commands will
reset the device to Read Array. The increased
number of cycles has been chosen to assure max-
imum data security. Instructions are initialised by
two initial Coded cycles which unlock the Com-
mand Interface. In addition, for Erase, instruction
confirmation is again preceded by the two Coded
cycles.
Status Register Bits
P/E.C. status is indicated during execution by Data
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt from any address during Pro-
gram or Erase command execution will automati-
cally output these five Status Register bits. The P/
E.C. automatically sets bits DQ2, DQ3, DQ5, DQ6
and DQ7. Other bits (DQ0, DQ1 and DQ4) are re-
served for future use and should be masked. See
Table 8.
Data Polling Bit (DQ7).
When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After com-
pletion of the operation, DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourth W pulse for programming or
after the sixth W pulse for erase. See Figure 11 for
the Data Polling waveforms and Figure 12 for the
Data Polling flowchart. A Valid Address is the ad-
dress being programmed or any address while
erasing the chip.
Toggle Bit (DQ6).
When Programming or Eras-
ing operations are in progress, successive at-
tempts to read DQ6 will output complementary
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| M59BW10225N1T | 1 Mbit 64Kb x16, Burst Low Voltage Flash Memory |
| M59BW102N | 1 Mbit 64Kb x16, Burst Low Voltage Flash Memory |
| M59DR008 | 8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR008E100N1T | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TV07; No. of Contacts:56; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Jam Nut Receptacle; Body Style:Straight |
| M59DR008E100N6T | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TV07; Number of Contacts:56; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Jam Nut Receptacle; Body Style:Straight |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M59BW10225N1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 64Kb x16, Burst Low Voltage Flash Memory |
| M59BW102N | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 64Kb x16, Burst Low Voltage Flash Memory |
| M59DR008 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR008E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR008E100N1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
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