參數(shù)資料
型號: M59BW102
廠商: 意法半導(dǎo)體
英文描述: 1 Mbit 64Kb x16, Burst Low Voltage Flash Memory
中文描述: 1兆位64Kb的x16插槽,突發(fā)低電壓快閃記憶體
文件頁數(shù): 10/24頁
文件大小: 181K
代理商: M59BW102
M59BW102
10/24
Table 11. DC Characteristics
(T
A
= 0 to 70°C; V
CC
= 3.0V to 3.6V)
Symbol
Note: 1. Sampled only, not 100% tested.
Table 12. Sequential Read Mode AC Characteristics
(
T
A
= 0 to 70°C)
Note: 1. This timing refers to a Load Capacitance (C
L
) of 30pF. If C
L
is higher, add 1 ns for each extra 10pF.
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
±1
μA
I
LO
Output Leakage Current
0V
V
OUT
V
CC
±1
μA
I
CC1
Supply Current (Read)
E = V
IL
, G = V
IH
, f = 6MHz
10
mA
I
CC2
Supply Current (Standby)
ALE, E = V
CC
± 0.2V
100
μA
I
CC3 (1)
Supply Current (Program or Erase)
Byte program or
Chip Erase in progress
20
mA
V
IL
Input Low Voltage
–0.5
0.8
V
V
IH
Input High Voltage
2
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 1.8mA
0.45
V
V
OH
Output High Voltage
I
Oh
= –100μA
V
CC
– 0.4V
V
V
ID
A9, E, G High Voltage
11.5
12.5
V
I
ID
A9, E, G High Current
A9, E, G = V
ID
100
μA
V
LKO (1)
Supply Voltage (Erase and Program
lock-out)
1.8
2.3
V
Symbol
Alt
Parameter
Test Condition
M59BW102
Unit
25
V
CC
= 3.0V to 3.6V
Min
Typ
Max
t
CYCLE
t
CY
Sequential Cycle
E = V
IL
, ALE = V
IL
25
ns
t
GHGL
t
GW
Output Enable High to Output Enable Low
G = Pulse
13
ns
t
GLGH
t
GL
Output Enable Low to Output Enable High
G = Pulse
12
ns
t
GHEL
t
ATT
Output Enable High to Chip Enable Low
–2
ns
t
GHEH
t
SBY
Output Enable High to Chip Enable High
–2
ns
t
EHALH
t
AV
Chip Enable High to Address Latch Enable
High
3
ns
t
GHALH
t
GS
Output Enable High to Address Latch
Enable High (following cycle)
0
ns
t
GHQV (1)
t
GACC
Output Enable High to Output Valid
20
ns
t
ELQV (1)
t
EACC
Chip Enable Low to Output Valid
20
ns
t
EHQZ
t
EDF
Chip Enable High to Output Hi-Z
12
ns
t
ALHQZ
t
ADF
Address Latch Enable High to Output Hi-Z
20
ns
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