303
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
(0x79)
ADCH
- / ADC9
- / ADC8
- / ADC7
- / ADC6
- / ADC5
- / ADC4
ADC9 /
ADC3
ADC8 /
ADC2
(0x78)
ADCL
ADC7 /
ADC1
ADC6 /
ADC0
ADC5 / -
ADC4 / -
ADC3 / -
ADC2 / -
ADC1 / -
ADC0 /
(0x77)
AMP2CSR
AMP2EN
AMP2IS
AMP2G1
AMP2G0
AMPCMP2
AMP2TS2
AMP2TS1
AMP2TS0
(0x76)
AMP1CSR
AMP1EN
AMP1IS
AMP1G1
AMP1G0
AMPCMP1
AMP1TS2
AMP1TS1
AMP1TS0
(0x75)
AMP0CSR
AMP0EN
AMP0IS
AMP0G1
AMP0G0
AMPCMP0
AMP0TS2
AMP0TS1
AMP0TS0
(0x74)
Reserved
–
(0x73)
Reserved
–
(0x72)
Reserved
–
(0x71)
Reserved
–
(0x70)
Reserved
–
(0x6F)
TIMSK1
–
–ICIE1
–
OCIE1B
OCIE1A
TOIE1
(0x6E)
TIMSK0
–
OCIE0B
OCIE0A
TOIE0
(0x6D)
PCMSK3
–
PCINT26
PCINT25
PCINT24
(0x6C)
PCMSK2
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
(0x6B)
PCMSK1
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
(0x6A)
PCMSK0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
(0x69)
EICRA
ISC31
ISC30
ISC21
ISC20
ISC11
ISC10
ISC01
ISC00
(0x68)
PCICR
–
PCIE3
PCIE2
PCIE1
PCIE0
(0x67)
Reserved
–
(0x66)
OSCCAL
–
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
(0x65)
Reserved
–
(0x64)
PRR
–
PRCAN
PRPSC
PRTIM1
PRTIM0
PRSPI
PRLIN
PRADC
(0x63)
Reserved
–
(0x62)
Reserved
–
(0x61)
CLKPR
CLKPCE
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
(0x60)
WDTCSR
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
0x3F (0x5F)
SREG
I
T
H
S
V
N
Z
C
0x3E (0x5E)
SPH
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
0x3D (0x5D)
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
0x3C (0x5C)
Reserved
–
0x3B (0x5B)
Reserved
–
0x3A (0x5A)
Reserved
–
0x39 (0x59)
Reserved
–
29.
Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega16/32/64/M1/C1 is a complex microcontroller with more peripheral units than can be supported within the 64 loca-
tion reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
5. These registers are only available on ATmega32/64M1. For other products described in this datasheet, these locations are
reserved.