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參數(shù)資料
| 型號(hào)： | M44C090-XXX-DIT |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, UUC |
| 封裝： | CHIP |
| 文件頁數(shù)： | 163/319頁 |
| 文件大?。?/td> | 11009K |
| 代理商： | M44C090-XXX-DIT |
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245
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the status register is set (one), the SPM ready interrupt will be enabled.
The SPM ready interrupt will be executed as long as the SPMEN bit in the SPMCSR register is cleared.
Bit 6 – RWWSB: Read-while-write Section Busy
When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by
hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE
bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will automatically be cleared
if a page load operation is initiated.
Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from
the signature row into the destination register. see Section 24.7.10 “Reading the Signature Row from Software” on page 249 for
details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This operation is reserved for
future use and should not be used.
Bit 4 – RWWSRE: Read-while-write Section Read Enable
When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will
be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN
will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four
clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while the flash is busy with a page erase or
a page write (SPMEN is set). If the RWWSRE bit is written while the flash is being loaded, the flash load operation will abort and
the data loaded will be lost.
Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets boot lock bits and
memory lock bits, according to the data in R0. The data in R1 and the address in the Z-pointer are ignored. The BLBSET bit will
automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles.
An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR register, will read either the Lock bits
or the fuse bits (depending on Z0 in the Z-pointer) into the destination register. See Section 24.7.9 “Reading the Fuse and Lock
Bits from Software” on page 248 for details.
Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write,
with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and
R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four
clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.
Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase.
The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear
upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the
entire Page Write operation if the NRWW section is addressed.
Bit 0 – SPMEN: Self Programming Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET,
PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written,
the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of
the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is
executed within four clock cycles. during page erase and page write, the SPMEN bit remains high until the operation is
completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no effect.
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