301
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
(0xBB)(5)
PIM
–
PEVE2
PEVE1
PEVE0
PEOPE
(0xBA)(5)
PMIC2
POVEN2
PISEL2
PELEV2
PFLTE2
PAOC2
PRFM22
PRFM21
PRFM20
(0xB9)(5)
PMIC1
POVEN1
PISEL1
PELEV1
PFLTE1
PAOC1
PRFM12
PRFM11
PRFM10
(0xB8)(5)
PMIC0
POVEN0
PISEL0
PELEV0
PFLTE0
PAOC0
PRFM02
PRFM01
PRFM00
(0xB7)(5)
PCTL
PPRE1
PPRE0
PCLKSEL
–
PCCYC
PRUN
(0xB6)(5)
POC
–
POEN2B
POEN2A
POEN1B
POEN1A
POEN0B
POEN0A
(0xB5)(5)
PCNF
–
PULOCK
PMODE
POPB
POPA
–
(0xB4)(5)
PSYNC
–
PSYNC21
PSYNC20
PSYNC11
PSYNC10
PSYNC01
PSYNC00
(0xB3)(5)
POCR_RBH
–
POCR_RB11 POCR_RB10 POCR_RB9 POCR_RB8
(0xB2)(5)
POCR_RBL POCR_RB7 POCR_RB6 POCR_RB5 POCR_RB4 POCR_RB3 POCR_RB2 POCR_RB1 POCR_RB0
(0xB1)(5)
POCR2SBH
–
POCR2SB11 POCR2SB10 POCR2SB9 POCR2SB8
(0xB0)(5)
POCR2SBL POCR2SB7 POCR2SB6 POCR2SB5 POCR2SB4 POCR2SB3 POCR2SB2 POCR2SB1 POCR2SB0
(0xAF)(5)
POCR2RAH
–
POCR2RA11 POCR2RA10 POCR2RA9 POCR2RA8
(0xAE)(5)
POCR2RAL POCR2RA7 POCR2RA6 POCR2RA5 POCR2RA4 POCR2RA3 POCR2RA2 POCR2RA1 POCR2RA0
(0xAD)(5)
POCR2SAH
–
POCR2SA11 POCR2SA10 POCR2SA9 POCR2SA8
(0xAC)(5)
POCR2SAL POCR2SA7 POCR2SA6 POCR2SA5 POCR2SA4 POCR2SA3 POCR2SA2 POCR2SA1 POCR2SA0
(0xAB)(5)
POCR1SBH
–
POCR1SB11 POCR1SB10 POCR1SB9 POCR1SB8
(0xAA)(5)
POCR1SBL POCR1SB7 POCR1SB6 POCR1SB5 POCR1SB4 POCR1SB3 POCR1SB2 POCR1SB1 POCR1SB0
(0xA9)(5)
POCR1RAH
–
POCR1RA11 POCR1RA10 POCR1RA9 POCR1RA8
(0xA8)(5)
POCR1RAL POCR1RA7 POCR1RA6 POCR1RA5 POCR1RA4 POCR1RA3 POCR1RA2 POCR1RA1 POCR1RA0
(0xA7)(5)
POCR1SAH
–
POCR1SA11 POCR1SA10 POCR1SA9 POCR1SA8
(0xA6)(5)
POCR1SAL POCR1SA7 POCR1SA6 POCR1SA5 POCR1SA4 POCR1SA3 POCR1SA2 POCR1SA1 POCR1SA0
(0xA5)(5)
POCR0SBH
–
POCR0SB11 POCR0SB10 POCR0SB9 POCR0SB8
(0xA4)(5)
POCR0SBL POCR0SB7 POCR0SB6 POCR0SB5 POCR0SB4 POCR0SB3 POCR0SB2 POCR0SB1 POCR0SB0
(0xA3)(5)
POCR0RAH
–
POCR0RA11 POCR0RA10 POCR0RA9 POCR0RA8
(0xA2)(5)
POCR0RAL POCR0RA7 POCR0RA6 POCR0RA5 POCR0RA4 POCR0RA3 POCR0RA2 POCR0RA1 POCR0RA0
(0xA1)(5)
POCR0SAH
–
POCR0SA11 POCR0SA10 POCR0SA9 POCR0SA8
(0xA0)(5)
POCR0SAL POCR0SA7 POCR0SA6 POCR0SA5 POCR0SA4 POCR0SA3 POCR0SA2 POCR0SA1 POCR0SA0
(0x9F)
Reserved
–
(0x9E)
Reserved
–
(0x9D)
Reserved
–
(0x9C)
Reserved
–
(0x9B)
Reserved
–
(0x9A)
Reserved
–
29.
Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega16/32/64/M1/C1 is a complex microcontroller with more peripheral units than can be supported within the 64 loca-
tion reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
5. These registers are only available on ATmega32/64M1. For other products described in this datasheet, these locations are
reserved.