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參數(shù)資料
| 型號(hào)： | M44C090-XXX-DIT |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, UUC |
| 封裝： | CHIP |
| 文件頁數(shù)： | 117/319頁 |
| 文件大?。?/td> | 11009K |
| 代理商： | M44C090-XXX-DIT |
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203
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
18.5.1 ADC Input Channels
When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is
selected:
●
In single conversion mode, always select the channel before starting the conversion. The channel selection may be
changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to
complete before changing the channel selection.
●
In free running mode, always select the channel before starting the first conversion. The channel selection may be
changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion
to complete, and then change the channel selection. Since the next conversion has already started automatically, the
next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection.
●
In free running mode, because the amplifier clear the ADSC bit at the end of an amplified conversion, it is not possible to
use the free running mode, unless ADSC bit is set again by soft at the end of each conversion.
Note:
When The ADC and COMPARATOR share the same channel (possible configuration for AMP1+, AMP1- and
AMP2-), up to revision B of ATmega32M1 the comparator is disconnected during the sampling of the ADC. For
ATmega16/64 and ATmega32 revision C, the COMPARATOR is always connected.
18.5.2 ADC Voltage Reference
The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF
will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 2.56V reference, or external AREF pin.
AVCC is connected to the ADC through a passive switch. The internal 2.56V reference is generated from the internal bandgap
reference (VBG) through an internal amplifier. In either case, the external AREF pin is directly connected to the ADC, and the
reference voltage can be made more immune to noise by connecting a capacitor between the AREF pin and ground. VREF can
also be measured at the AREF pin with a high impedant voltmeter. Note that VREF is a high impedant source, and only a
capacitive load should be connected in a system.
If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in
the application, as they will be shorted to the external voltage. If no external voltage is applied to the AREF pin, the user may
switch between AVCC and 2.56V as reference selection. The first ADC conversion result after switching reference voltage
source may be inaccurate, and the user is advised to discard this result.
AREF pin is alternate function with ISRC current source output. When current source is selected, the AREF pin is not connected
to the internal reference voltage network. See AREFEN and ISRCEN bits in Section 18.9.3 “ADC control and status register B–
If differential channels are used, the selected reference should not be closer to AVCC than indicated in Table 26-6 on page 280.
18.6
ADC Noise Canceler
The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and
other I/O peripherals. The noise canceler can be used with ADC noise reduction and Idle mode. To make use of this feature, the
following procedure should be used:
●
Make sure the ADATE bit is reset.
●
Make sure that the ADC is enabled and is not busy converting. Single conversion mode must be selected and the ADC
conversion complete interrupt must be enabled.
●
Enter ADC noise reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted.
●
If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute
the ADC conversion complete interrupt routine. If another interrupt wakes up the CPU before the ADC conversion is
complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the
ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC noise
reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power
consumption.
If the ADC is enabled in such sleep modes and the user wants to perform differential conversions, the user is advised to switch
the ADC off and on after waking up from sleep to prompt an extended conversion to get a valid result.
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