Addressing mode
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
ZP, IND
IND, X
IND, Y
REL
SP
7
6
5
4
3
2
1
0
Processor status register
NV
T
B
D
I
Z
C
OP n# OP n# OP n# OP n# OP n
# OP n# OP n#
OP n#
OP n# OP n
#
3886 Group User’s Manual
3-77
APPENDIX
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
IMM
A
BIT, A
ZP
BIT, ZP
OP n# OP n# OP n# OP n# OP n#
OP n
#
3-76
APPENDIX
3886 Group User’s Manual
3.7 Machine instructions
75
35
16
4
6
2
6D
2D
0E
2C
4
6
4
3
7D
3D
1E
5
7
3
79
39
5
3
61
21
6
2
90
B0
F0
2
71
31
6
2
N
M7
V
M6
Z
Z
C
C
When T = 0, this instruction adds the contents
M, C, and A; and stores the results in A and C.
When T = 1, this instruction adds the contents
of M(X), M and C; and stores the results in
M(X) and C. When T=1, the contents of A re-
main unchanged, but the contents of status
flags are changed.
M(X) represents the contents of memory
where is indicated by X.
When T = 0, this instruction transfers the con-
tents of A and M to the ALU which performs a
bit-wise AND operation and stores the result
back in A.
When T = 1, this instruction transfers the con-
tents M(X) and M to the ALU which performs a
bit-wise AND operation and stores the results
back in M(X). When T = 1 the contents of A re-
main unchanged, but status flags are
changed.
M(X) represents the contents of memory
where is indicated by X.
This instruction shifts the content of A or M by
one bit to the left, with bit 0 always being set to
0 and bit 7 of A or M always being contained in
C.
This instruction tests the designated bit i of M
or A and takes a branch if the bit is 0. The
branch address is specified by a relative ad-
dress. If the bit is 1, next instruction is
executed.
This instruction tests the designated bit i of the
M or A and takes a branch if the bit is 1. The
branch address is specified by a relative ad-
dress. If the bit is 0, next instruction is
executed.
This instruction takes a branch to the ap-
pointed address if C is 0. The branch address
is specified by a relative address. If C is 1, the
next instruction is executed.
This instruction takes a branch to the ap-
pointed address if C is 1. The branch address
is specified by a relative address. If C is 0, the
next instruction is executed.
This instruction takes a branch to the ap-
pointed address when Z is 1. The branch
address is specified by a relative address.
If Z is 0, the next instruction is executed.
This instruction takes a bit-wise logical AND of
A and M contents; however, the contents of A
and M are not modified.
The contents of N, V, Z are changed, but the
contents of A, M remain unchanged.
This instruction takes a branch to the ap-
pointed address when N is 1. The branch
address is specified by a relative address.
If N is 0, the next instruction is executed.
This instruction takes a branch to the ap-
pointed address if Z is 0. The branch address
is specified by a relative address. If Z is 1, the
next instruction is executed.
ADC
(Note 1)
(Note 5)
AND
(Note 1)
ASL
BBC
(Note 4)
BBS
(Note 4)
BCC
(Note 4)
BCS
(Note 4)
BEQ
(Note 4)
BIT
BMI
(Note 4)
BNE
(Note 4)
7
0
C
←
←0
29 2
2
0A 2
1
03
+
20i
17
+
20i
07
+
20i
06 5
2
25 3
2
3
65 3
2
69 2
2
4
2
13
+
20i
5
3
24
When T = 0
A
← A + M + C
When T = 1
M(X)
← M(X) + M + C
When T = 0
A
← A M
When T = 1
M(X)
← M(X) M
Ai or Mi = 0?
Ai or Mi = 1?
C = 0?
C = 1?
Z = 1?
A
M
N = 1?
Z = 0?
V
2
3.7 Machine instructions
BIT, A, R
BIT, ZP, R
30
D0
2