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3886 Group User’s Manual
HARDWARE
(3) Flash memory mode 3 (CPU reprogramming
mode)
The M38869FFAHP/GP has the CPU reprogramming mode where
a built-in flash memory is handled by the central processing unit
(CPU).
In CPU reprogramming mode, the flash memory is handled by
writing and reading to/from the flash memory control register (see
Figure 81) and the flash command register (see Figure 82).
The CNVSS pin is used as the VPP power supply pin in CPU repro-
gramming mode. It is necessary to apply the power-supply voltage
of VPPH from the external to this pin.
Functional Outline (CPU reprogramming mode)
Figure 81 shows the flash memory control register bit configura-
tion. Figure 82 shows the flash command register bit
configuration.
Bit 0 of the flash memory control register is the CPU reprogram-
ming mode select bit. When this bit is set to “1” and VPPH is
applied to the CNVss/VPP pin, the CPU reprogramming mode is
selected. Whether the CPU reprogramming mode is realized or
not is judged by reading the CPU reprogramming mode monitor
flag (bit 2 of the flash memory control register).
Bit 1 is a busy flag which becomes “1” during erase and program
execution.
Whether each operation has been completed or not is judged by
checking this flag after execution of each erase or program com-
mand.
Bits 4, 5 of the flash memory control register are the erase/pro-
gram area select bits. These bits specify an area where erase and
program is operated. When the erase command is executed after
an area is specified by these bits, only the specified area is
erased. Programming is enabled only for the specified area: pro-
gramming is disabled for all other areas.
When CPU reprogramming mode is valid, the area not specified
by the erase/program area select bits cannot be read out.
Transfer the CPU reprogramming mode control program to inter-
nal RAM before entering the CPU reprogramming mode, and then
execute this program on internal RAM.
If an interrupt occurs while this program is being executed, the
flash memory area is accessed, but normal operations cannot be
performed because the flash memory area cannot be read out.
Execute processes such as interrupt disable during the CPU re-
programming mode control program.
Figure 83 shows the CPU mode register bit configuration in the
CPU reprogramming mode. Set bits 1 and 0 to “00” (single-chip
mode) in the CPU reprogramming mode.
Fig. 81 Flash memory control register bit configuration
FUNCTIONAL DESCRIPTION
7
6
543
2
1
0
Flash memory control register
(FCON : address 0FFE16)
CPU reprogramming mode select bit (Note)
0 : CPU reprogramming mode is invalid. (Normal operation mode)
1 : When applying 0 V or VPPL to CNVSS/VPP pin, CPU reprogramming mode is
invalid. When applying VPPH to CNVSS/VPP pin, CPU reprogramming mode is valid.
Erase/Program busy flag
0 : Erase and program are completed or not have been executed.
1 : Erase/program is being executed.
CPU reprogramming mode monitor flag
0 : CPU reprogramming mode is invalid.
1 : CPU reprogramming mode is valid.
Erase/Program area select bits
0 0 : Addresses 100016 to FFFF16 (total 60 Kbytes)
0 1 : Addresses 100016 to 7FFF16 (total 28 Kbytes)
1 0 : Addresses 800016 to FFFF16 (total 32 Kbytes)
1 1 : Not available
Fix this bit to “0.”
Note: Bit 0 can be reprogrammed only when 0 V is applied to the CNVSS/VPP pin.
Not used (returns "0" when read)