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3886 Group User’s Manual
2.5 Multi-master I2C-BUS interface
APPLICATION
(2)
Procedure for generating START condition using multi-master
Procedure example (The necessary conditions for the procedure are described in Items to
below).
LDA #SLADR
(Take out slave address value)
SEI
(Disable interrupt)
BBS 5, S1, BUSBUSY (BB flag confirmation and branch process)
BUSFREE:
STA S0
(Write slave address value)
LDM #$F0, S1
(Trigger START condition generation)
CLI
(Enable interrupt)
:
BUSBUSY:
CLI
(Enable interrupt)
:
Use “Branch on Bit Set” of “BBS 5, S1, –” for the BB flag confirmation and branch process.
Use “STA”, “STX” or “STY” of the zero page addressing instruction for writing the slave address
value to the I2C data shift register (S0: address 001216).
Execute the branch instruction of above and the store instruction of above continuously shown
the above procedure example.
Disable interrupts during the following three process steps:
BB flag confirmation
Write slave address value
Trigger START condition generation
When the BB flag is in bus busy state, enable interrupts immediately.
(3)
Procedure for generating RESTART condition
This procedure cannot be applied to M38867M8A and M38867E8A when the external memory is
used and the bus cycle is extended by ONW function.
Procedure example (The necessary conditions for the procedure are described in Items to
below). Execute the following procedure when the PIN bit is “0”.
LDM #$00, S1
(Select slave receive mode)
LDA #SLADR
(Take out slave address value)
SEI
(Disable interrupt)
STA S0
(Write slave address value)
LDM #$F0, S1
(Trigger RESTART condition generation)
CLI
(Enable interrupt)
:
Select the slave receive mode when the PIN bit is “0”. Do not write “1” to the PIN bit. Neither “0” nor
“1” is specified as input to the BB bit. The TRX bit becomes “0” and the SDA pin is released.
The SCL pin is released by writing the slave address value to the I2C data shift register.
Disable interrupts during the following two process steps:
Write slave address value
Trigger RESTART condition generation
(4)
Writing to I2C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and
TRX bits to “0” from “1” simultaneously. Because it may enter the state that the SCL pin is released
and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the
MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1”. Because it may become
the same as above.