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| 型號(hào)： | M38049FFLSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PDIP64 |
| 封裝： | 17 X 56.40 MM, 1.78 MM HEIGHT, PLASTIC, SDIP-64 |
| 文件頁(yè)數(shù)： | 99/129頁(yè) |
| 文件大?。?/td> | 1721K |
| 代理商： | M38049FFLSP |
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Rev.1.00
Oct 27, 2008
Page 71 of 128
REJ03B0266-0100
3804 Group (Spec.L)
[I2C START/STOP Condition Control Register (S2D)]
001616
The I2C START/STOP condition control register (S2D: address
001616) controls START/STOP condition detection.
Bits 0 to 4: START/STOP condition set bits
(SSC4-SSC0)
SCL release time, setup time, and hold time change the detection
condition by value of the main clock divide ratio selection bit
and the oscillation frequency f(XIN) because these time are
measured by the internal system clock. Accordingly, set the
proper value to the START/STOP condition set bits (SSC4 to
SSC0) in considered of the system clock frequency. Refer to
Do not set “000002” or an odd number to the START/STOP
condition set bits (SSC4 to SSC0).
Refer to Table 14, the recommended set value to START/STOP
condition set bits (SSC4-SSC0) for each oscillation frequency.
Bit 5: SCL/SDA interrupt pin polarity selection bit
(SIP)
An interrupt can occur when detecting the falling or rising edge
of the SCL or SDA pin. This bit selects the polarity of the SCL or
SDA pin interrupt pin.
Fig. 70 Structure of I2C START/STOP condition control
register
Bit 6: SCL/SDA interrupt pin selection bit (SIS)
This bit selects the pin of which interrupt becomes valid between
the SCL pin and the SDA pin.
Note. When changing the setting of the SCL/SDA interrupt pin polarity
selection bit, the SCL/SDA interrupt pin selection bit, or the I2C-
BUS interface enable bit ES0, the SCL/SDA interrupt request bit
may be set. When selecting the SCL/SDA interrupt source, dis-
able the interrupt before the SCL/SDA interrupt pin polarity selec-
tion bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS
interface enable bit ES0 is set. Reset the request bit to “0” after
setting these bits, and enable the interrupt.
NOTE:
1. Do not set an odd number to the START/STOP condition set bits (SSC4 to SSC0) and “000002”.
SIS
SIP SSC4 SSC3 SSC2 SSC1 SSC0
I2C START/STOP condition
control register
(S2D: address 001616)
START/STOP condition set bits
SCL/SDA interrupt pin polarity
selection bit
0: Falling edge active
1: Rising edge active
SCL/SDA interrupt pin selection bit
0: SDA valid
1: SCL valid
b7
b0
Not used
(Fix this bit to “0”.)
Table 14 Recommended set value to START/STOP condition set bits (SSC4-SSC0) for each oscillation frequency
Oscillation
frequency
f(XIN)(MHz)
Main clock
divide ratio
Internal clock
φ
(MHz)
START/STOP
condition control
register
SCL release time
(
μs)
Setup time
(
μs)
Hold time
(
μs)
82
4
XXX11010
6.75
μs (27 cycles)
3.5
μs (14 cycles)
3.25
μs (13 cycles)
XXX11000
6.25
μs (25 cycles) 3.25 μs (13 cycles)
3.0
μs (12 cycles)
8
1
XXX00100
5.0
μs (5 cycles)
3.0
μs (3 cycles)
2.0
μs (2 cycles)
42
2
XXX01100
6.5
μs (13 cycles)
3.5
μs (7 cycles)
3.0
μs (6 cycles)
XXX01010
5.5
μs (11 cycles)
3.0
μs (6 cycles)
2.5
μs (5 cycles)
2
1
XXX00100
5.0
μs (5 cycles)
3.0
μs (3 cycles)
2.0
μs (2 cycles)
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