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參數(shù)資料
| 型號(hào)： | M38049FFLSP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PDIP64 |
| 封裝： | 17 X 56.40 MM, 1.78 MM HEIGHT, PLASTIC, SDIP-64 |
| 文件頁(yè)數(shù)： | 49/129頁(yè) |
| 文件大?。?/td> | 1721K |
| 代理商： | M38049FFLSP |
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Rev.1.00
Oct 27, 2008
Page 26 of 128
REJ03B0266-0100
3804 Group (Spec.L)
Fig. 20 Interrupt control diagram
Interrupt Disable Flag
The interrupt disable flag is assigned to bit 2 of the processor
status register. This flag controls the acceptance of all interrupt
requests except for the BRK instruction. When this flag is set to
“1”, the acceptance of interrupt requests is disabled. When it is
set to “0”, acceptance of interrupt requests is enabled. This flag is
set to “1” with the SET instruction and set to “0” with the CLI
instruction.
When an interrupt request is accepted, the contents of the
processor status register are pushed onto the stack while the
interrupt disable flag remains set to “0”. Subsequently, this flag is
automatically set to “1” and multiple interrupts are disabled. To
use multiple interrupts, set this flag to “0” with the CLI
instruction within the interrupt processing routine.
The contents of the processor status register are popped off the
stack with the RTI instruction.
Interrupt Request Bits
Once an interrupt request is generated, the corresponding
interrupt request bit is set to “1” and remains “1” until the request
is accepted . Wh en the reques t is accepted, th is bit is
automatically set to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to
“1”, by software.
Interrupt Enable Bits
The interrupt enable bits control the acceptance of the
corresponding interrupt requests. When an interrupt enable bit is
set to “0”, the acceptance of the corresponding interrupt request
is disabled. If an interrupt request occurs in this condition, the
corresponding interrupt request bit is set to “1”, but the interrupt
request is not accepted. When an interrupt enable bit is set to “1”,
acceptance of the corresponding interrupt request is enabled.
Each interrupt enable bit can be set to “0” or “1” by software.
The interrupt enable bit for an unused interrupt should be set to
“0”.
Interrupt Source Selection
Any of the following combinations can be selected by the
interrupt source selection register (003916).
1. INT0 or timer Z
2. Serial I/O1 transmission or SCL, SDA
3. CNTR0 or SCL, SDA
4. CNTR1 or Serial I/O3 reception
5. Serial I/O2 or timer Z
6. INT2 or I2C
7. INT4 or CNTR2
8. A/D conversion or serial I/O3 transmission
External Interrupt Pin Selection
For external interrupts INT0 and INT4, the INT0, INT4 interrupt
switch bit in the interrupt edge selection register (bit 6 of address
003A16) can be used to select INT00 and INT40 pin input or
INT01 and INT41 pin input.
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
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| M38049RLSS | 功能描述:DEV EMULATOR CHIP RAM 2KB 64SDIP RoHS:否 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 內(nèi)電路編程器、仿真器以及調(diào)試器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 19/Jul/2010 標(biāo)準(zhǔn)包裝:1 系列:* 類(lèi)型:* 適用于相關(guān)產(chǎn)品:* 所含物品:* |
| M3806 | 功能描述:電纜固定件和配件 LTSCG 625 BLACK RoHS:否 制造商:Heyco 類(lèi)型:Cable Grips, Liquid Tight 材料:Nylon 顏色:Black 安裝方法:Cable 最大光束直徑:11.4 mm 抗拉強(qiáng)度: |
| M3806 BK001 | 制造商:Alpha Wire Company 功能描述:CBL 8COND 18AWG BLK 1000' |
| M3806 BK002 | 制造商:Alpha Wire Company 功能描述:CBL 8COND 18AWG BLK 500' |
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