![](http://datasheet.mmic.net.cn/90000/M38049FFLWG_datasheet_3496278/M38049FFLWG_64.png)
Rev.1.00
Oct 27, 2008
REJ03B0266-0100
3804 Group (Spec.L)
[I2C Data Shift Register (S0)] 001116
The I2C data shift register (S0: address 001116) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to
the outside from bit 7 in synchronization with the SCL, and each
time one-bit data is output, the data of this register are shifted by
one bit to the left. When data is received, it is input to this
register from bit 0 in synchronization with the SCL, and each
time one-bit data is input, the data of this register are shifted by
one bit to the left. The minimum 2 cycles of the internal clock
φ
are required from the rising of the SCL until input to this register.
The I2C data shift register is in a write enable status only when
the I2C-BUS interface enable bit (ES0 bit) of the I2C control
register (S1D: address 001416) is “1”. The bit counter is reset by
a write instruction to the I2C data shift register. When both the
ES0 bit and the MST bit of the I2C status register (S1: address
001316) are “1”, the SCL is output by a write instruction to the
I2C data shift register. Reading data from the I2C data shift
register is always enabled regardless of the ES0 bit value.
[I2C Slave Address Registers 0 to 2 (S0D0 to S0D2)]
0FF716 to 0FF916
The I2C slave address registers 0 to 2 (S0D0 to S0D2: addresses
0FF716 to 0FF916) consists of a 7-bit slave address and a read/
write bit. In the addressing mode, the slave address written in this
register is compared with the address data to be received
immediately after the START condition is detected.
Bit 0: Read/write bit (RWB)
This is not used in the 7-bit addressing mode. In the 10-bit
addressing mode, set RWB to “0” because the first address data
to be received is compared with the contents (SAD6 to SAD0 +
RWB) of the I2C slave address registers 0 to 2.
When 2-byte address data match slave address, a 7-bit slave
address which is received after restart condition has detected and
R/W data can be matched by setting “1” to RWB with software.
The RWB is cleared to “0” automatically when the stop
condition is detected.
Bits 1 to 7: Slave address (SAD0-SAD6)
These bits store slave addresses. Regardless of the 7-bit
addressing mode or the 10-bit addressing mode, the address data
transmitted from the master is compared with these bits’
contents.
Fig. 61 Structure of I2C slave address registers 0 to 2
I2C slave address register 0
(S0D0: address 0FF716)
I2C slave address register 1
(S0D1: address 0FF816)
I2C slave address register 2
(S0D2: address 0FF916)
Read/write bit
Slave address
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB
b0
b7