
M37920F8CGP, M37920F8CHP, M37920FCCGP
M37920FCCHP, M37920FGCGP, M37920FGCHP
19
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
X
0
X
0
AD1 (A1)
Even-numbered address
4-byte boundary
8-byte boundary
BIU Functions
(1) Instruction prefetch
The BIU has ten instruction queue buffers; each buffer consists of 1
byte. When there is an opening in the bus and the instruction queue
buffer, an instruction code is read from the program memory (in other
words, the memory where a program is stored) and prefetched into
an instruction queue buffer. The prefetched instruction code is trans-
ferred from the BIU to the CPU, in response to a request from the
CPU, via a dedicated bus.
When a branch occurs as a result of a branch instruction (JMP, BRA,
etc.), subroutine call, or interrupt, the contents of the instruction
queue buffer are initialized and the BIU reads a new instruction from
the branch destination address.
Note that the operations of the BIU instruction prefetch also differ de-
pending on the store addresses for instructions. The store addresses
for instructions to be prefetched are categorized as listed in Table 2.
(2) Data read operation
When executing an instruction for reading data from the internal
memory, internal peripheral devices, or external areas, at first, the
CPU informs the BIU’s data address register of the address where
the data has been located.
Next, the BIU reads the above data from the specified address,
passes it to the data buffer, and then, transfers it to the CPU.
(3) Data write operation
When executing an instruction for writing data into the internal
memory, internal peripheral devices, or external area, at first, the
CPU informs the BIU’s data address register of the address where
the data has been located.
Next, the BIU passes the above data to the data buffer register, and
then, writes it into the specified address.
(4) Bus cycle
In order for the BIU to execute the above operations (1) through (3),
the 24-bit address bus, 32-bit code bus, 16-bit data bus and internal
control signals must be appropriately controlled during data transfer
between the BIU and internal memory, internal peripheral devices,
external areas. This operation is called “bus cycle”. The bus cycle is
affected by the following conditions at instruction prefetch and data
access.
[Instruction prefetch]
Whether the address area locates in the internal area or the ex-
ternal area.
When the address area locates in the external area
Whether the bus width of external devices = 16 bits or 8 bits:
(a) When the external bus width = 16 bits:
whether the start address for access locates at a 4-
byte boundary or at an 8-byte boundary.
(b) When the external bus width = 8 bits:
whether the start address for access locates at an
even-numbered address, a 4-byte boundary or at the 8-
byte bound ary.
Whether the prefetch operation is generated by a branch, or
not.
Number of waits
Others: Whether any the burst ROM access and the DRAM
space is specified or not. (For details, refer to the section on
the chip select wait controller and DRAM controller described
later.)
Table 2. Store addresses for instructions to be prefetched
Low-order 3 bits of store address for instruction
AD2 (A2)
0
AD0 (A0)
[Data Access]
Whether the address area locates in the internal area or the ex-
ternal area.
Length of data to be transferred: byte, word, double word
When the address area locates in the external area:
Whether the bus width of external devices = 16 bits or 8 bits:
Number of waits
Others: Whether the DRAM space is specified or not. (For
details, refer to the section on the chip select wait controller
and DRAM controller described later.)
The BIU controls the bus cycle depending on the above conditions.
Instruction prefetch and data access are performed as shown in
Tables 3 to 10.
X: 0 or 1