參數(shù)資料
型號: M37920F8CHP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 121/155頁
文件大?。?/td> 1274K
代理商: M37920F8CHP
M37920F8CGP, M37920F8CHP, M37920FCCGP
M37920FCCHP, M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
68
A-D CONVERTER
The A-D converter is a 10-bit successive approximation converter.
Figure 63 shows the block diagram of the A-D converter, Figure 64
shows the bit configuration of the A-D control register 0 (address
1E16), and the bit configuration of the A-D control register 1 (address
1F16).
A-D conversion accuracy
Bit 3 of A-D control register 1 is used to select whether to regard the
conversion result as 10-bit or as 8-bit data. The conversion result is
regarded as 10-bit data when bit 3 is “1” and as 8-bit data when bit 3
is “0”.
When the conversion result is used as 10-bit data, the low-order 8
bits of the conversion result is stored in the even-numbered address
of the corresponding A-D register and the high-order 2 bits are
stored in bits 0 and 1 at the odd-numbered address of the corre-
sponding A-D register. Bits 2 to 7 of the A-D register odd-numbered
Fig. 63 A-D converter block diagram
address are “0000002” when read.
When the conversion result is used as 8-bit data, the conversion re-
sult are stored in even-numbered address of the corresponding A-D
register. In this case, the value at the A-D register’s odd-numbered
address is “0016” when read.
A-D conversion frequency
An operation clock (
φAD) of an A-D converter can be selected with bit
7 of the A-D control register 0 and bit 4 of the A-D control register 1.
When bit 4 of the A-D control register 1 is “0”,
φAD becomes f2/4
when bit 7 of the A-D control register 0 is “0”,
φAD becomes f2/2 when
bit 7 of the A-D control register 0 is “1”.
When bit 4 of the A-D control register 1 is “1”,
φAD becomes f2 when
bit 7 of the A-D control register 0 is “0”,
φAD becomes f1 when bit 7 of
the A-D control register 0 is “1”. Note that
φAD = f1 (in other words,
the fastest speed) can be selected only in the 8-bit mode.
φAD during A-D conversion must be 250 kHz or more because the
comparator uses a capacity coupling amplifier.
Data bus (even)
Selector
Successive approximation register
Decoder
A-D control register 0 (Address 1E16)
Ladder network
VREF
AVSS
Vref
AN0
AN1
AN2
AN3/ADTRG
Comparator
A-D register 0 (Address 2016)
A-D register 1 (Address 2216)
A-D register 2 (Address 2416)
A-D register 3 (Address 2616)
A-D register 0 (Address 2116)
A-D register 1 (Address 2316)
A-D register 2 (Address 2516)
A-D register 3 (Address 2716)
Data bus (odd)
A-D control register 1 (Address 1F16)
1/2
f2
φAD
A-D conversion frequency selection
f1
VREF connection select bit
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