83
M37920F8CGP, M37920F8CHP, M37920FCCGP
M37920FCCHP, M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
Transfer address direction
The address direction in DMA transfers can be designated indepen-
dently for the transfer source and destination. These directions are
available: “forward”, “backward”, and “fixed”. When the forward di-
rection is selected, the address increments. When the backward di-
rection is selected, the address decrements. When the fixed
direction is selected, the address is fixed (2 bytes when 1 transfer
unit consists of 16 bits, or 1 byte when 1 transfer unit consists of 8
bits) and does not change. Use bits 4 and 5 of the DMAi mode regis-
ter L shown in Figure 69 to specify the transfer address direction for
the transfer source. For the transfer destination, use bits 6 and 7.
Figure 77 shows an example of transfer address direction in the 2-
bus cycle transfer (1 transfer unit = 16 bits). Figure 77-(1) shows an
example when the transfer source address direction is “forward” and
the destination addresses are “fixed”. In this setup, the transfer
source memory’s data is called up in the forward address direction
and written to the transfer destination memory’s fixed address by the
“1 transfer unit”. Figure 77-(2) shows an example when both the
transfer source and destination address directions are set to “for-
ward” by using the DMAi mode register L. In this type of setup, data
are transferred from the transfer source memory to the transfer des-
tination memory in the sequence of , , , .... Figure 77-(3) shows
an example when the transfer source address direction is “forward”
and the destination address direction is “backward”. Figure 77-(4)
shows an example when the transfer source address direction is
“backward” and the destination address is “fixed”. In this setup, the
transfer source memory’s data is written to the fixed transfer desti-
nation memory’s address by the “1 transfer unit” in the sequence of
, , and ....
As explained above, in 2-bus cycle transfer, three different address
directions are selectable for each of the transfer source and destina-
tion. A total of nine different address direction combinations are avail-
able.
In 1-bus cycle transfer, the memory side’s address direction depends
on the memory bits. For data transfer from memory to external I/O,
therefore, use bits 4 and 5 (transfer-source-address-direction select
bits) of the DMAi mode register L to determine the memory side’s
(transfer source) address direction. This is not affected by bits 6 and
7 (transfer-destination-address-direction select bits). For data trans-
fer from external I/O to memory, use bits 6 and 7 of the DMAi mode
register L to determine the memory side’s (transfer destination) ad-
dress direction. This is not affected by bits 4 and 5.