M37920F8CGP, M37920F8CHP, M37920FCCGP
M37920FCCHP, M37920FGCGP, M37920FGCHP
17
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
BUS INTERFACE UNIT
Data transfer shown below is always performed via the bus interface
unit (BIU), which is located between the CPU and the internal buses:
Between the CPU and the internal memory, internal peripheral de-
vices, external areas
Between the DMA controller (DMAC) and the internal memory, in-
ternal peripheral devices, external areas
Figure 7 shows the BIU and the bus structure. The CPU and BIU, or
DMAC and BIU are connected by a dedicated bus respectivery, and
any transfer between the CPU and BIU, or DMAC and BIU is con-
trolled by this dedicated bus.
On the other hand, data transfer between the BIU and internal pe-
ripheral devices uses the following internal common buses: 32-bit
code bus, 16-bit data bus, 24-bit address bus, and control signals.
The bus control method where the code bus and the data bus sepa-
rate out (hereafter, this method is referred to as the separate code/
data bus method) is employed in order to improve data transfer ca-
Fig. 7 BIU and bus structure
Internal code bus (CB0 to CB31)
Central
Processing
Unit
(CPU)
SFR : Special Function Register
g The CPU bus, DMAC bus, internal bus, and external bus separate out independently.
External
devices
Internal control signal
CPU bus
Internal bus
Internal data bus (DB0 to DB15)
Internal
memory
Internal
peripheral
devices
(SFR)
External bus
A0 to A23 (MA0 to MA11)
D0 to D7
D8 to D15
Control signal
Bus
Interface
Unit
(BIU)
Bus
conversion
circuit
Internal address bus (AD0 to AD23)
DMA
controller
(DMAC)
DMAC bus
Refresh request
DRAM control signal
DRAM
controller
(DRAMC)
HOLD
Hold request
HLDA
pabilities. As a result, the internal memory is connected to both the
code bus and the data bus, and registers of all other internal periph-
eral devices are connected only to the data bus.
Each width of external buses are as follows: a 24-bit address bus,
16-bit data bus.
The external data bus transfers instruction codes and data. When
the code or data access occurs for the external, the external access
is performed via the bus conversion circuit.
When the DRAM is selected in external devices, the internal DMAC
controller (DRAMC) is operated, and access for DRAM and DRAM
refresh operation become enabled. For details, refer to the section
on the chip select wait controller and DRAMC described later.
When accessing the external devices, it is possible to insert the re-
covery cycles. Refer to the section on the processor modes and chip
select wait controller described later.
When the burst ROM is used as an external device, refer to the sec-
tion on the chip select wait controller described later.