參數(shù)資料
型號(hào)： M37735MHBXXXFP
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 6/93頁(yè)
文件大?。?/td> 1802K
代理商： M37735MHBXXXFP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
11
MITSUBISHI MICROCOMPUTERS
M37735MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When performing 16-bit data read or write, waveform (2) is used to
access each byte one by one if the conditions for simultaneously
accessing two bytes are not satisfied. However, when prefetching
the instruction code, if the address of the instruction code is odd,
waveform (1) is used, and only one byte is read in the instruction
queue buffer.
Access to the even/odd address is controlled by signals BHE and A0.
Signal BHE is not directly output to the outside, but write signals (WEL,
WEH
) are generated corresponding to the accessed address (even
or odd).
Bit 2 of processor mode register 0 (address 5E16) is the wait bit.
When the external memory area is accessed in the memory expansion
mode or the microprocessor mode with this bit set to “0”, the width of
the E signal is extended and access time can be extended.
There are two ways to extend the access time and they are selected
with bit 0 of the processor mode register 1 (address 5F16).
When this bit is set to “1”, the “L” width of the E signal in (1) becomes
twice as long as in (3) and the access time becomes 1.5 times (wait
1). When this bit is set to “0”, the ALE signal and E signal in (1) are
extended as in (7) and the access time is doubled (wait 0).
However, these signals are not extended when accessing the internal
memory area.
When the wait bit is set to “1”, these signals are not extended when
accessing any memory area regardless of the bit 0 of the processor
mode register 1.
Waveforms (4), (5), and (6) show the entire waveform, first half, and
last half respectively of waveform (2) for wait 1.
Waveforms (8), (9), and (10) show the entire waveform, first half,
and last half respectively of waveform (2) for wait 0.
Instruction code read, data read, and data write are described below.
Instruction code read will be described first.
The CPU obtains instruction codes from the instruction queue buffer
and executes them. The CPU notifies the bus interface unit that it is
requesting an instruction code during an instruction code request
cycle. If the requested instruction code is not yet stored in the
instruction queue buffer, the bus interface unit halts the CPU until
more instructions than requested is stored in the instruction queue
buffer. Even if there is no instruction code request from the CPU, the
bus interface unit reads instruction codes from the memory and stores
them in the instruction queue buffer when the instruction queue buffer
is empty or when only one instruction code is stored and the bus is
idle on the next cycle. This is referred to as instruction pre-fetching.
Normally , when reading an instruction code from the memory, if the
accessed address is even, the next odd address is read together
with the instruction code and stored in the instruction queue buffer.
However, in the memory expansion mode or the microprocessor
mode, only one byte is read and stored in the instruction queue buffer
if the following conditions are satisfied.
The address to be read is in the external memory area when the
external data bus has an 8-bit width (BYTE = “H”).
The address to be read is odd.
Therefore, waveform (1), (3) or (7) in Figure 5 is used for instruction
code read. Data read and write are described below.
The CPU notifies the bus interface unit when performing data read or
write. At this time, the bus interface unit halts the CPU if the bus
interface unit is already using the bus or if there is a request with
higher priority. When data read or write is enabled, the bus interface
unit uses one of the waveforms from (1) to (10) in Figure 5 to perform
the operation.
During data read, the CPU waits until the entire data is stored in the
data buffer. The bus interface unit sends the address received from
the CPU to the address bus. Then it reads the memory when the E
signal is “L” and stores the result in the data buffer.
During data write, the CPU writes the data in the data buffer and the
bus interface unit writes it to the memory . Therefore, the CPU can
proceed to the next step without waiting for write completed. The bus
interface unit sends the address received from the CPU to the address
bus. Then when the E signal is “L”, the bus interface unit sends the
data in the data buffer to the data bus and writes it to the memory.
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參數(shù)描述
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