- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45037 > M37735MHBXXXFP 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP80 PDF資料下載
參數(shù)資料
| 型號： | M37735MHBXXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 51/93頁 |
| 文件大小： | 1802K |
| 代理商： | M37735MHBXXXFP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁當(dāng)前第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁
52
MITSUBISHI MICROCOMPUTERS
M37735MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
CS0
to CS4 are the chip select signals and are “L” when the address
shown in Table 7 is accessed. RSMP is the ready-sampling signal
which is output for the RDY input described later when the external
memory area is accessed. By inputting logical AND of RSMP and
CSn
(n = 0 to 4) to the RDY pin, read/write term for any address areas
can be extended by 1 cycle of clock
φ 1. In addition, the read/write
term can also be extended by 2 cycles of clock
φ 1 if the above
function and wait 0/1 function specified with the wait bit are used
together.
Port P1 has two functions depending on the level of the BYTE pin.
In bose cases, the I/O port function is lost.
When the BYTE pin level is “L”, port P1 functions as an address (A15
to A8) output pin while RDE or WEL, WEH are “H” and as an odd
address data I/O pin while these signals are “L”. However, if an internal
memory is read, external data is ignored while RDE is “L”.
When the BYTE pin level is “H”, port P1 functions as an address
output pin.
Port P2 has two functions depending on the level of the BYTE pin.
In bose cases, the I/O port function is lost.
When the BYTE pin level is “L”, port P2 functions as an address (A0
to A7) output pin while RDE or WEL, WEH are “H” and as an even
address data I/O pin while these signals are “L”. However, if an internal
memory is read, external data is ignored while RDE is “L”.
When the BYTE pin level is “H”, port P2 functions as an address (A0
to A7) output pin while RDE or WEL, WEH are “H” and as an even and
odd address data I/O pin while these signals are “L”. However, if an
internal memory is read, external data is ignored while RDE is “L”.
Ports P30, P31, P32, and P33 become WEL, WEH, ALE, and HLDA
output pins, respectively and lose their I/O port functions.
WEL
, WEH are the write-enable low signal and the write-enable high
signal, respectively. These signals go “L” during the data write term
of the write cycle, but their operations differ depending on the BYTE
pin level.
In the case the BYTE pin level is “L”, WEL is “L” when writing to
an even address, WEH is “L” when writing to an odd address, and
both WEL and WEH are “L” when writing to even and odd addresses.
In the case the BYTE pin level is “H”, regardless of address, only
WEL
is “L”, and WEH retains “H”. WEL and WEH can also be fixed to
“H” when the internal memory is accessed, same as RDE, by writing
“1” to the signal output disable selection bit.
ALE is an address latch enable signal used to latch the address signal
from a multiplexed signal of address and data. The latch is transparent
while ALE is “H” to let the address signal pass through and held
while ALE is “L”.
HLDA
is a hold acknowledge signal and is used to notify externally
when the microcomputer receives HOLD input and enters into hole
state.
Ports P40 and P41 become HOLD and RDY input pin, respectively,
and lose their output pin function.
HOLD
is a hold request signal. It is an input signal used to put the
microcomputer in hold state. HOLD input is accepted when the internal
clock
φ falls from “H” level to “L” level while the bus is not used.
Ports P0, P1, P2, P30, P31, and pin E/RDE are floating while the
microcomputer stays in hold state. These ports become floating after
one cycle of internal clock
φ later than HLDA signal changes to “L”
level. At releasing hold state, these ports are released from floating
state after one cycle of internal clock
φ later than HLDA signal changes
to “H” level.
RDY
is a ready signal. If this signal goes “L”, the internal clock
φ
stops at “L”. RDY is used when slow external memory is attached.
Port P42 becomes a normal I/O port when bit 7 of the processor
mode register 0 is “0” and becomes an output pin for clock
φ 1 when
bit 7 is “1”. The
φ 1 output is independent of RDY and does not stop
even when internal clock
φ stops because of “L” input to the RDY
pin.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37735MHLXXXHP | 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80 |
| M37735S4LHP | 16-BIT, 12 MHz, MICROCONTROLLER, PQFP80 |
| M37736EHBGS | 16-BIT, UVPROM, 24 MHz, MICROCONTROLLER, CQCC100 |
| M37736EHBXXXGP | 16-BIT, OTPROM, 25 MHz, MICROCONTROLLER, PQFP100 |
| M37736EHBGS | 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CQCC100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37735MHL | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37735MHL-143HP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:PROM VERSION OF M37735MHLXXXHP |
| M37735MHLXXXHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37735S4BFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:16-BIT CMOS MICROCOMPUTER |
| M37735S4LHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:16-BIT CMOS MICROCOMPUTER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。