參數(shù)資料
型號: M37735MHBXXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù): 40/93頁
文件大?。?/td> 1802K
代理商: M37735MHBXXXFP
42
MITSUBISHI MICROCOMPUTERS
M37735MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
(1) One-shot mode
One-shot mode is selected when bits 3 and 4 of A-D control register
0 are “0”. The analog input pin (AN0 – AN7) is selected with bits 0 to
2 of A-D control register 0. A-D conversion can be started by a software
trigger or by an external trigger.
A software trigger is selected when bit 5 of A-D control register 0 is
“0” and an external trigger is selected when it is “1”. When a software
trigger is selected, A-D conversion is started when bit 6 (A-D
conversion start flag) is set to “1”. A-D conversion ends after 59
φ AD
cycles and an interrupt request bit of the A-D conversion interrupt
control register is set to “1”. At the same time, the A-D conversion
start flag (bit 6 of the A-D control register 0) is cleared and A-D
conversion stops. The result of A-D conversion is stored in the A-D
register corresponding to the selected pin.
If an external trigger is selected, A-D conversion starts when the A-D
conversion start flag is “1” and the ADTRG input changes from “H” to
“L”. In this case, the pins that can be used for A-D conversion are
AN0 to AN4, AN6 and AN7 (a total of 7) because the ADTRG pin is also
used as the analog voltage input pin (AN5). The operation is the same
as with software trigger except that the A-D conversion start flag is
not cleared after A-D conversion and a retrigger can be available
during A-D conversion.
(2) Repeat mode
Repeat mode is selected when bit 3 of A-D control register 0 is “1”
and bit 4 is “0”. The operation of this mode is the same as the operation
of one-shot mode except that when A-D conversion of the selected
pin is complete and the result is stored in the A-D register, conversion
does not stop, but is repeated.
No interrupt request is issued in this mode. Furthermore, if software
trigger is selected, the A-D conversion start flag is not cleared.
The contents of the A-D register can be read at any time.
Fig. 50 A-D control register bit configuration
76
543
2
0
1
0
Address
1F16
A-D control register 1
A-D sweep pin selection bits
0 0 : AN0, AN1
(2 pins)
0 1 : AN0 – AN3 (4 pins)
1 0 : AN0 – AN5 (6 pins)
1 1 : AN0 – AN7 (8 pins)
0 : Always “0”
VREF connection selection bit
0 : VREF is connected
1 : VREF is not connected
Analog input selection bits
0 0 0 : Select AN0
0 0 1 : Select AN1
0 1 0 : Select AN2
0 1 1 : Select AN3
1 0 0 : Select AN4
1 0 1 : Select AN5
1 1 0 : Select AN6
1 1 1 : Select AN7
A-D operation mode selection bits
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode
76
543
2
0
1
A-D control register 0
Trigger selection bit
0 : Software trigger
1 : ADTRG input trigger
A-D conversion start flag
0 : Stop A-D conversion
1 : Start A-D conversion
A-D conversion frequency (
φ AD) selection flag
0 : Select f2/4
1 : Select f2/2
1E16
Address
8/10-bit mode selection bit
0 : 8-bit mode
1 : 10-bit mode
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