7
MITSUBISHI MICROCOMPUTERS
M37735MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
CENTRAL PROCESSING UNIT (CPU)
The CPU has ten registers and is shown in Figure 3. Each of these
registers is described below.
ACCUMULATOR A (A)
Accumulator A is the main register of the microcomputer. It consists
of 16 bits and the low-order 8 bits can be used separately. The data
length flag (m) determines whether the register is used as a 16-bit
register or as an 8-bit register. It is used as a 16-bit register when flag
m is “0” and as an 8-bit register when flag m is “1”. Flag m is a part of
the processor status register (PS) which is described later.
Data operations such as arithmetic operation, data transfer, input/
output, etc., are executed mainly through the accumulator A.
ACCUMULATOR B (B)
Accumulator B has the same functions as accumulator A, but the
use of accumulator B requires more instruction bytes and execution
cycles than accumulator A.
INDEX REGISTER X (X)
Index register X consists of 16 bits and the low-order 8 bits can be
used separately. The index register length flag (x) determines whether
the register is used as a 16-bit register or as an 8-bit register. It is
used as a 16-bit register when flag x is “0” and as an 8-bit register
when flag x is “1”. Flag x is a part of the processor status register
(PS) which is described later.
In an index addressing mode where register X is used as the index
register, the contents of this address is added to obtain the real
address.
Also, when executing a block transfer instruction (MVP, MVN), the
contents of index register X indicates the low-order 16 bits of the
source data address. The third byte of the MVP or MVN is the high-
order 8 bits of the source data address.
INDEX REGISTER Y (Y)
Index register Y consists of 16 bits and the low-order 8 bits can be
used separately. The index register length flag (x) determines whether
the register is used as a 16-bit register or as an 8-bit register. It is
used as a 16-bit register when flag x is “0” and as an 8-bit register
when flag x is “1”. Flag x is a part of the processor status register
(PS) which is described later.
In an index addressing mode where register Y is used as the index
register, the contents of this address is added to obtain the real
address.
Also, when executing a block transfer instruction (MVP, MVN), the
contents of index register Y indicates the low-order 16 bits of the
destination data address. The second byte of the MVP or MVN is the
high-order 8 bits of the destination data address.
Fig. 3 Register structure
7
0
PG
Program bank register (PG)
7
0
DT
Data bank register (DT)
Carry flag
Zero frag
Interrupt disable flag
Decimal mode flag
Index register length flag
Data length flag
Negative flag
Overflow flag
Processor interrupt priority level (IPL)
Accumulator A (A)
Accumulator B (B)
Index register X (X)
Index register Y (Y)
Stack pointer (S)
Program counter (PC)
Direct page register (DPR)
Processor status register (PS)
0
AH
AL
15
0
7
BH
BL
15
0
7
XH
XL
15
0
7
YH
YL
15
0
7
15
0
PC
15
0
15
0
DPR
7
15
0
N
IPL2
IPL0
IPL1
C
Z
I
D
x
m
V
00 00
S