參數(shù)資料
型號: M37373M8-XXXSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP52
封裝: 0.600 INCH, 1.778 MM PITCH, SHRINK, PLASTIC, DIP-52
文件頁數(shù): 41/110頁
文件大?。?/td> 1537K
代理商: M37373M8-XXXSP
36
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37273M8-XXXSP
M37273E8SP
Fig. 32. Sync Pulse Counter Register
(13) Synchronous Signal Counter
The synchronous signal counter counts the composite sync signal
taken out from a video signal in the data slicer circuit or the vertical
synchronous signal Vsep as a count source.
The count value in a certain time (T time) generated by f(XIN)/213 or
f(XIN)/213 is stored into the 5-bit latch. Accordingly, the latch value
changes in the cycle of T time. When the count value exceeds “1F16,”
“1F16” is stored into the latch.
The latch value can be obtained by reading out the sync pulse counter
register (address 00E916). A count source is selected by bit 5 of the
sync pulse counter register.
The synchronous signal counter is used when bit 0 of PWM mode
register 1 (address 020816).
Figure 32 shows the structure of the sync pulse counter and Figure
33 shows the synchronous signal counter block diagram.
Fig. 33. Synchronous Signal Counter Block Diagram
Sync pulse counter register
(HC : address 00E9 16)
Count value
Count source
Count time
0: HSYNC
signal
1: Composite
sync signal
f(XIN)/213
(1024 s, f(XIN) = 8 MHz)
70
Reset
5-bit counter
Latch (5 bits)
f(XIN)/213
Composite
sync signal
HSYNC signal
Counter
Sync pulse
counter register
Data bus
Selection gate : connected to black
side when reset.
b5
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