
33
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37273M8-XXXSP
M37273E8SP
Field and Line to Generate Slice Voltage
Field specified by bit 1 of DSC1
Line 21 (total 1 line)
Field specified by bit 1 of DSC1
A line specified by bits 4 to 0 of CPS
(total 1 line) (See note 3)
Field specified by bit 1 of DSC1
Line 21 (total 1 line)
Field specified by bit 1 of DSC1
Line 21 and a line specified by bits 4 to 0 of CPS
(total 2 lines) (See note 2)
Field and Line to Be Sliced Data
Both fields of F1 and F2
Line 21 and a line specified by bits 4 to 0 of CPS
(total 2 lines) (See note 2)
Both fields of F1 and F2
A line specified by bits 4 to 0 of CPS
(total 1 line) (See note 3)
Both fields of F1 and F2
Line 21 (total 1 line)
Both fields of F1 and F2
Line 21 and a line specified by bits 4 to 0 of CPS
(total 2 lines) (See note 2)
CPS
b7
0
1
b6
0
1
0
1
Notes 1: DSC is data slicer control register 1.
CPS is caption position register.
2: Set “0016” to “1D16” to bits 4 to 0 of CPS.
3: Set “0016” to “1F16” to bits 4 to 0 of CPS.
Table 3. Specification of Data Slice Line
(7) Reference Voltage Generating Circuit and
Comparator
The composite video signal clamped by the clamping circuit is input
to the reference voltage generating circuit and the comparator.
Reference Voltage Generating Circuit
This circuit generates a reference voltage (slice voltage) by using
the amplitude of the clock run-in pulse in line specified by the data
slice line specification circuit. Connect a capacitor between the
VHOLD pin and the VSS pin, and make the length of wiring as short
as possible so that a leakage current may not be generated.
Comparator
The comparator compares the voltage of the composite video
signal with the voltage (reference voltage) generated in the
reference voltage generating circuit, and converts the composite
video signal into a digital value.
(8) Start Bit Detecting Circuit
This circuit detects a start bit at line decided in the data slice line
specification circuit.
The detection of a start bit is described below.
A sampling clock is generated by dividing the reference clock
output by the timing signal.
A clock run-in pulse is detected by the sampling clock.
After detection of the pulse, a start bit pattern is detected from the
comparator output.
(9) Clock run-in Determination Circuit
This circuit determinates clock run-in by counting the number of pulses
in a window of the composite video signal.
The reference clock count value in one pulse cycle is stored in bits 3
to 7 of the clock run-in detect register (address 00E416). Read out
these bits after the occurence of a data slicer interrupt (refer to (12)
Interrupt Request Generating Circuit).
Figure 30 shows the structure of clock run-in detect register.
Fig. 30. Clock Run-in Detect Register
70
Clock run-in detection bit
Number of reference clocks to
be counted in one clock run-in
pulse period
Clock run-in detect register
(CRD : address 00E4 16)
Test bits : read-only