參數(shù)資料
型號: M37373M8-XXXSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP52
封裝: 0.600 INCH, 1.778 MM PITCH, SHRINK, PLASTIC, DIP-52
文件頁數(shù): 110/110頁
文件大?。?/td> 1537K
代理商: M37373M8-XXXSP
99
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37273M8-XXXSP
M37273E8SP
Sync Pulse Counter Register
Data Clock Position Register
Caption Position Register
b7 b6 b5 b4 b3 b2 b1 b0
Data clock position register (DPS) [Address 00E5 16]
Data Clock Position Register
0
2
1
0
RW
3
Data clock position set
bits (DPS3 to DPS7)
1R W
Fix these bits to “0.“
1
Fix this bit to “1.“
0R W
10
0
B
After reset
Functions
Name
RW
4
to
7
0
b7 b6 b5 b4 b3 b2 b1 b0
Caption Position Register (CPS) [Address 00E6 16]
Caption Position Register
0
to
4
0R W
Caption position bits
(CPS0 to CPS4)
6, 7
Refer to the corresponding
Table (P33).
Slice line mode
specification bits
(in 1 field) (CPS6, CPS7)
5
0: Data is not latched yet and a
clock-run-in is not determined.
1: Data is latched and a
clock-run-in is determined.
Caption data latch
completion flag 2
(CPS1)
Indetermined R—
B
After reset
Functions
Name
RW
b7 b6 b5 b4 b3 b2 b1 b0
Sync pulse counter register (HC) [Address 00E916]
R W
Sync Pulse Counter Register
0
to
4
0R —
6, 7
0
R —
Count value (HC0 to HC4)
5
0R W
Count source (HC5)
0: HSYNC signal
1: Composite sync signal
B
After reset
Functions
Name
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Address 00E516
Address 00E616
Address 00E916
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