參數(shù)資料
型號： M37373M8-XXXSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP52
封裝： 0.600 INCH, 1.778 MM PITCH, SHRINK, PLASTIC, DIP-52
文件頁數(shù)： 25/110頁
文件大?。?/td> 1537K
代理商： M37373M8-XXXSP
21
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37273M8-XXXSP
M37273E8SP
Fig. 15. Serial I/O Mode Register
Internal clock: The serial I/O counter is set to “7” during the write
cycle into the serial I/O register (address 00EA16), and the transfer
clock goes HIGH forcibly. At each falling edge of the transfer clock
after the write cycle, serial data is output from the SOUT pin. Transfer
direction can be selected by bit 5 of the serial I/O mode register. At
each rising edge of the transfer clock, data is input from the SIN pin
and data in the serial I/O register is shifted 1 bit.
After the transfer clock has counted 8 times, the serial I/O counter
becomes “0” and the transfer clock stops at HIGH. At this time the
interrupt request bit is set to “1.”
External clock: When an external clock is selected as the clock source,
the interrupt request is set to “1” after the transfer clock has been
counted 8 counts. However, transfer operation does not stop, so the
clock should be controlled externally. Use the external clock of 500kHz
or less with a duty cycle of 50%.
The serial I/O timing is shown in Figure 14. When using an external
clock for transfer, the external clock must be held at HIGH for initial-
izing the serial I/O counter. When switching between an internal clock
and an external clock, do not switch during transfer. Also, be sure to
initialize the serial I/O counter after switching.
Notes 1: On programming, note that the serial I/O counter is set by
writing to the serial I/O register with the bit managing in-
structions, such as SEB and CLB.
2: When an external clock is used as the synchronous clock,
write transmit data to the serial I/O register when the trans-
fer clock input leve is HIGHl.
Fig. 14. Serial I/O Timing (for LSB first)
Synchronous clock
Transfer clock
Serial I/O register
write signal
Serial I/O output
SOUT
D0
D1
D2
D3
D4
D5
D6
D7
(Note)
Serial I/O input
SIN
Note : When an internal clock is selected, the S OUT pin is at high-impedance after transfer is completed.
Interrupt request bit is set to “1”
7
Serial I/O mode register
(SM : address 00EB16)
Internal synchronous clock
selection bits
b1 b0
0
0 : f(XIN)/8 or f(XCIN)/8
0
1 : f(XIN)/16 or f(XCIN)/16
1
0 : f(XIN)/32 or f(XCIN)/32
1
1 : f(XIN)/64 or f(XCIN)/64
0
Synchronous clock selection bit
0 : External clock
1 : Internal clock
Fix this bit to “0”
Transfer direction selection bit
0 : LSB first
1 : MSB first
0
Fix this bit to “0”
Transger clock input pin selection bit
0 : Input signal from S IN pin
1 : Input signal from S OUT pin
Port function selection bit
0 : P20, P21
1 : SCLK, SOUT
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