參數(shù)資料
型號: M36WT864T70ZA6T
廠商: 意法半導(dǎo)體
英文描述: 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product
中文描述: 64兆位4Mb的x16插槽,多銀行,突發(fā)閃存和8兆位的SRAM為512k x16,內(nèi)存產(chǎn)品多
文件頁數(shù): 75/92頁
文件大?。?/td> 624K
代理商: M36WT864T70ZA6T
75/92
M36WT864TF, M36WT864BF
Note: 1. The variable P is a pointer which is defined at CFI offset 15h.
2. Bank Regions. There are two Bank Regions, Region 1 contains all the banks that are made up of main blocks only, Region 2 con-
tains the banks that are made up of the parameter and main blocks.
(P+34)h =6Dh
03h
(P+3C)h =75h
03h
Bank Region 2 (Erase Block Type 1): Page mode and
synchronous
mode capabilities (defined in table 10)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+35)h =6Eh
07h
Bank Region 2 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
(P+36)h =6Fh
00h
(P+37)h =70h
02h
(P+38)h =71h
00h
(P+39)h =72h
64h
Bank Region 2 (Erase Block Type 2)
Minimum block erase cycles × 1000
(P+3A)h =73h
00h
(P+3B)h =74h
01h
Bank Region 2 (Erase Block Type 2): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
(P+3C)h =75h
03h
Bank Region 2 (Erase Block Type 2): Page mode and
synchronous
mode capabilities (defined in table 10)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+3D)h =76h
(P+3D)h =76h
Feature Space definitions
(P+3E)h =77h
(P+3E)h =77h
Reserved
M36WT864TF (top)
M36WT864BF (bottom)
Description
Offset
Data
Offset
Data
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PDF描述
M36WT864TFZA 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product
M36WT864BFZA 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product
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